commit 0b118206bf3411722707f2e5cab8fd2eedcd50d6
author Reid Spencer <rspencer@reidspencer.com> Mon Jan 16 21:12:35 2006 +0000
committer Reid Spencer <rspencer@reidspencer.com> Mon Jan 16 21:12:35 2006 +0000
tree 1a222f39010130f9e1a5a30f5937bf323b7265eb
parent e86bf519e1ea57a84d37422ec364f89c322e3ef4

For PR411:
This patch is an incremental step towards supporting a flat symbol table.
It de-overloads the intrinsic functions by providing type-specific intrinsics
and arranging for automatically upgrading from the old overloaded name to
the new non-overloaded name. Specifically:
  llvm.isunordered -> llvm.isunordered.f32, llvm.isunordered.f64
  llvm.sqrt -> llvm.sqrt.f32, llvm.sqrt.f64
  llvm.ctpop -> llvm.ctpop.i8, llvm.ctpop.i16, llvm.ctpop.i32, llvm.ctpop.i64
  llvm.ctlz -> llvm.ctlz.i8, llvm.ctlz.i16, llvm.ctlz.i32, llvm.ctlz.i64
  llvm.cttz -> llvm.cttz.i8, llvm.cttz.i16, llvm.cttz.i32, llvm.cttz.i64
New code should not use the overloaded intrinsic names. Warnings will be
emitted if they are used.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25366 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 31b7fc7..cd4250b 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -963,12 +963,14 @@
       setValue(&I, DAG.getNode(ISD::UNDEF, TLI.getValueType(I.getType())));
     return 0;
     
-  case Intrinsic::isunordered:
+  case Intrinsic::isunordered_f32:
+  case Intrinsic::isunordered_f64:
     setValue(&I, DAG.getSetCC(MVT::i1,getValue(I.getOperand(1)),
                               getValue(I.getOperand(2)), ISD::SETUO));
     return 0;
     
-  case Intrinsic::sqrt:
+  case Intrinsic::sqrt_f32:
+  case Intrinsic::sqrt_f64:
     setValue(&I, DAG.getNode(ISD::FSQRT,
                              getValue(I.getOperand(1)).getValueType(),
                              getValue(I.getOperand(1))));
@@ -996,17 +998,26 @@
                              getValue(I.getOperand(1)).getValueType(),
                              getValue(I.getOperand(1))));
     return 0;
-  case Intrinsic::cttz:
+  case Intrinsic::cttz_i8:
+  case Intrinsic::cttz_i16:
+  case Intrinsic::cttz_i32:
+  case Intrinsic::cttz_i64:
     setValue(&I, DAG.getNode(ISD::CTTZ,
                              getValue(I.getOperand(1)).getValueType(),
                              getValue(I.getOperand(1))));
     return 0;
-  case Intrinsic::ctlz:
+  case Intrinsic::ctlz_i8:
+  case Intrinsic::ctlz_i16:
+  case Intrinsic::ctlz_i32:
+  case Intrinsic::ctlz_i64:
     setValue(&I, DAG.getNode(ISD::CTLZ,
                              getValue(I.getOperand(1)).getValueType(),
                              getValue(I.getOperand(1))));
     return 0;
-  case Intrinsic::ctpop:
+  case Intrinsic::ctpop_i8:
+  case Intrinsic::ctpop_i16:
+  case Intrinsic::ctpop_i32:
+  case Intrinsic::ctpop_i64:
     setValue(&I, DAG.getNode(ISD::CTPOP,
                              getValue(I.getOperand(1)).getValueType(),
                              getValue(I.getOperand(1))));