Fix CellSPU vector shuffles, again.
Some cases of lowering to rotate were miscompiled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113355 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/test/CodeGen/CellSPU/shuffles.ll b/test/CodeGen/CellSPU/shuffles.ll
index f37d2ae..94b5fbd 100644
--- a/test/CodeGen/CellSPU/shuffles.ll
+++ b/test/CodeGen/CellSPU/shuffles.ll
@@ -39,3 +39,29 @@
ret <4 x float> %rv
}
+define <2 x i32> @test_v2i32(<4 x i32>%vec)
+{
+;CHECK: rotqbyi $3, $3, 4
+;CHECK: bi $lr
+ %rv = shufflevector <4 x i32> %vec, <4 x i32> undef, <2 x i32><i32 1,i32 2>
+ ret <2 x i32> %rv
+}
+
+define <4 x i32> @test_v4i32_rot8(<4 x i32>%vec)
+{
+;CHECK: rotqbyi $3, $3, 8
+;CHECK: bi $lr
+ %rv = shufflevector <4 x i32> %vec, <4 x i32> undef,
+ <4 x i32> <i32 2,i32 3,i32 0, i32 1>
+ ret <4 x i32> %rv
+}
+
+define <4 x i32> @test_v4i32_rot4(<4 x i32>%vec)
+{
+;CHECK: rotqbyi $3, $3, 4
+;CHECK: bi $lr
+ %rv = shufflevector <4 x i32> %vec, <4 x i32> undef,
+ <4 x i32> <i32 1,i32 2,i32 3, i32 0>
+ ret <4 x i32> %rv
+}
+