Make fsel emission work with both the pattern and dag-dag selectors, by
giving it a non-instruction opcode.  The dag->dag selector used to not
select the operands of the fsel, because it thought that whole tree was
already selected.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23091 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp
index 7d46477..d84552c 100644
--- a/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -125,34 +125,34 @@
           std::swap(TV, FV);  // fsel is natively setge, swap operands for setlt
         case ISD::SETUGE:
         case ISD::SETGE:
-          return DAG.getTargetNode(PPC::FSEL, ResVT, LHS, TV, FV);
+          return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV);
         case ISD::SETUGT:
         case ISD::SETGT:
           std::swap(TV, FV);  // fsel is natively setge, swap operands for setlt
         case ISD::SETULE:
         case ISD::SETLE:
-          return DAG.getTargetNode(PPC::FSEL, ResVT,
-                                   DAG.getNode(ISD::FNEG, ResVT, LHS), TV, FV);
+          return DAG.getNode(PPCISD::FSEL, ResVT,
+                             DAG.getNode(ISD::FNEG, ResVT, LHS), TV, FV);
         }
       
       switch (CC) {
       default: assert(0 && "Invalid FSEL condition"); abort();
       case ISD::SETULT:
       case ISD::SETLT:
-        return DAG.getTargetNode(PPC::FSEL, ResVT,
-                                 DAG.getNode(ISD::SUB, CmpVT, LHS, RHS), FV,TV);
+        return DAG.getNode(PPCISD::FSEL, ResVT,
+                           DAG.getNode(ISD::SUB, CmpVT, LHS, RHS), FV, TV);
       case ISD::SETUGE:
       case ISD::SETGE:
-        return DAG.getTargetNode(PPC::FSEL, ResVT,
-                                 DAG.getNode(ISD::SUB, CmpVT, LHS, RHS), TV,FV);
+        return DAG.getNode(PPCISD::FSEL, ResVT,
+                           DAG.getNode(ISD::SUB, CmpVT, LHS, RHS), TV, FV);
       case ISD::SETUGT:
       case ISD::SETGT:
-        return DAG.getTargetNode(PPC::FSEL, ResVT,
-                                 DAG.getNode(ISD::SUB, CmpVT, RHS, LHS), FV,TV);
+        return DAG.getNode(PPCISD::FSEL, ResVT,
+                           DAG.getNode(ISD::SUB, CmpVT, RHS, LHS), FV, TV);
       case ISD::SETULE:
       case ISD::SETLE:
-        return DAG.getTargetNode(PPC::FSEL, ResVT,
-                                 DAG.getNode(ISD::SUB, CmpVT, RHS, LHS), TV,FV);
+        return DAG.getNode(PPCISD::FSEL, ResVT,
+                           DAG.getNode(ISD::SUB, CmpVT, RHS, LHS), TV, FV);
       }
     }
     break;