Add codegen support for NEON vld3lane intrinsics with 128-bit vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83585 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp
index 39c253b..ba11f8c 100644
--- a/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -1577,18 +1577,73 @@
SDValue MemAddr, MemUpdate, MemOpc;
if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
return NULL;
+ if (VT.is64BitVector()) {
+ switch (VT.getSimpleVT().SimpleTy) {
+ default: llvm_unreachable("unhandled vld3lane type");
+ case MVT::v8i8: Opc = ARM::VLD3LNd8; break;
+ case MVT::v4i16: Opc = ARM::VLD3LNd16; break;
+ case MVT::v2f32:
+ case MVT::v2i32: Opc = ARM::VLD3LNd32; break;
+ }
+ SDValue Chain = N->getOperand(0);
+ const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
+ N->getOperand(3), N->getOperand(4),
+ N->getOperand(5), N->getOperand(6), Chain };
+ return CurDAG->getMachineNode(Opc, dl, VT, VT, VT, MVT::Other, Ops, 8);
+ }
+ // Quad registers are handled by extracting subregs, doing the load,
+ // and then inserting the results as subregs.
+ EVT RegVT;
+ unsigned Opc2 = 0;
switch (VT.getSimpleVT().SimpleTy) {
- default: llvm_unreachable("unhandled vld3lane type");
- case MVT::v8i8: Opc = ARM::VLD3LNd8; break;
- case MVT::v4i16: Opc = ARM::VLD3LNd16; break;
- case MVT::v2f32:
- case MVT::v2i32: Opc = ARM::VLD3LNd32; break;
+ default: llvm_unreachable("unhandled vld2lane type");
+ case MVT::v8i16:
+ Opc = ARM::VLD3LNq16a;
+ Opc2 = ARM::VLD3LNq16b;
+ RegVT = MVT::v4i16;
+ break;
+ case MVT::v4f32:
+ Opc = ARM::VLD3LNq32a;
+ Opc2 = ARM::VLD3LNq32b;
+ RegVT = MVT::v2f32;
+ break;
+ case MVT::v4i32:
+ Opc = ARM::VLD3LNq32a;
+ Opc2 = ARM::VLD3LNq32b;
+ RegVT = MVT::v2i32;
+ break;
}
SDValue Chain = N->getOperand(0);
- const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
- N->getOperand(3), N->getOperand(4),
- N->getOperand(5), N->getOperand(6), Chain };
- return CurDAG->getMachineNode(Opc, dl, VT, VT, VT, MVT::Other, Ops, 8);
+ unsigned Lane = cast<ConstantSDNode>(N->getOperand(6))->getZExtValue();
+ unsigned NumElts = RegVT.getVectorNumElements();
+ int SubregIdx = (Lane < NumElts) ? ARM::DSUBREG_0 : ARM::DSUBREG_1;
+
+ SDValue D0 = CurDAG->getTargetExtractSubreg(SubregIdx, dl, RegVT,
+ N->getOperand(3));
+ SDValue D1 = CurDAG->getTargetExtractSubreg(SubregIdx, dl, RegVT,
+ N->getOperand(4));
+ SDValue D2 = CurDAG->getTargetExtractSubreg(SubregIdx, dl, RegVT,
+ N->getOperand(5));
+ const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, D0, D1, D2,
+ getI32Imm(Lane % NumElts), Chain };
+ SDNode *VLdLn = CurDAG->getMachineNode((Lane < NumElts) ? Opc : Opc2,
+ dl, RegVT, RegVT, RegVT,
+ MVT::Other, Ops, 8);
+ SDValue Q0 = CurDAG->getTargetInsertSubreg(SubregIdx, dl, VT,
+ N->getOperand(3),
+ SDValue(VLdLn, 0));
+ SDValue Q1 = CurDAG->getTargetInsertSubreg(SubregIdx, dl, VT,
+ N->getOperand(4),
+ SDValue(VLdLn, 1));
+ SDValue Q2 = CurDAG->getTargetInsertSubreg(SubregIdx, dl, VT,
+ N->getOperand(5),
+ SDValue(VLdLn, 2));
+ Chain = SDValue(VLdLn, 3);
+ ReplaceUses(SDValue(N, 0), Q0);
+ ReplaceUses(SDValue(N, 1), Q1);
+ ReplaceUses(SDValue(N, 2), Q2);
+ ReplaceUses(SDValue(N, 3), Chain);
+ return NULL;
}
case Intrinsic::arm_neon_vld4lane: {