commit 0c2a4f39ad5cdb32a2c4e20f787798d8af645393
author Chris Lattner <sabre@nondot.org> Mon Jan 07 03:13:06 2008 +0000
committer Chris Lattner <sabre@nondot.org> Mon Jan 07 03:13:06 2008 +0000
tree bc7819e296dc7afa567f6fc31691d31f16381d48
parent 99aa33745d9f0a255da9e56315993e68997e1e21

Move a bunch more accessors from TargetInstrInfo to TargetInstrDescriptor


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45680 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/Mips/MipsInstrInfo.cpp

diff --git a/lib/Target/Mips/MipsInstrInfo.cpp b/lib/Target/Mips/MipsInstrInfo.cpp
index cda5052..8896b35 100644
--- a/lib/Target/Mips/MipsInstrInfo.cpp
+++ b/lib/Target/Mips/MipsInstrInfo.cpp
@@ -261,7 +261,7 @@
       unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm());
       const TargetInstrDescriptor &TID = get(Opc);
 
-      if (TID.numOperands == 3)
+      if (TID.getNumOperands() == 3)
         BuildMI(&MBB, TID).addReg(Cond[1].getReg())
                           .addReg(Cond[2].getReg())
                           .addMBB(TBB);
@@ -277,7 +277,7 @@
   unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm());
   const TargetInstrDescriptor &TID = get(Opc);
 
-  if (TID.numOperands == 3)
+  if (TID.getNumOperands() == 3)
     BuildMI(&MBB, TID).addReg(Cond[1].getReg())
                       .addReg(Cond[2].getReg())
                       .addMBB(TBB);