commit 0c922879854f5a6ee60283b99c68089f76f94778
author Vincent Lejeune <vljn@ovi.com> Mon Jun 03 15:56:12 2013 +0000
committer Vincent Lejeune <vljn@ovi.com> Mon Jun 03 15:56:12 2013 +0000
tree 3bd41a61832bfea7fbb720c2a418f1e15c71425e
parent fdf7ab1c69c3d6a68d312c52421c289b13d9eb5e

R600: 3 op instructions have no write bit but the result are store in PV

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183111 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/R600/R600Packetizer.cpp

diff --git a/lib/Target/R600/R600Packetizer.cpp b/lib/Target/R600/R600Packetizer.cpp
index 033c0b4..da614c7 100644
--- a/lib/Target/R600/R600Packetizer.cpp
+++ b/lib/Target/R600/R600Packetizer.cpp
@@ -80,9 +80,7 @@
       if (TII->isTransOnly(BI))
         continue;
       int OperandIdx = TII->getOperandIdx(BI->getOpcode(), R600Operands::WRITE);
-      if (OperandIdx < 0)
-        continue;
-      if (BI->getOperand(OperandIdx).getImm() == 0)
+      if (OperandIdx > -1 && BI->getOperand(OperandIdx).getImm() == 0)
         continue;
       unsigned Dst = BI->getOperand(0).getReg();
       if (BI->getOpcode() == AMDGPU::DOT4_r600 ||