diff --git a/lib/Target/X86/FloatingPoint.cpp b/lib/Target/X86/FloatingPoint.cpp
index ceb3bf6..ab6d77b 100644
--- a/lib/Target/X86/FloatingPoint.cpp
+++ b/lib/Target/X86/FloatingPoint.cpp
@@ -614,7 +614,7 @@
   delete MI;   // Remove the old instruction
 }
 
-/// handleCompareFP - Handle FpUCOM and FpUCOMI instructions, which have two FP
+/// handleCompareFP - Handle FUCOM and FUCOMI instructions, which have two FP
 /// register arguments and no explicit destinations.
 /// 
 void FPS::handleCompareFP(MachineBasicBlock::iterator &I) {
@@ -623,7 +623,7 @@
   MachineInstr *MI = I;
 
   unsigned NumOperands = MI->getNumOperands();
-  assert(NumOperands == 2 && "Illegal FpUCOM* instruction!");
+  assert(NumOperands == 2 && "Illegal FUCOM* instruction!");
   unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
   unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1));
   bool KillsOp0 = false, KillsOp1 = false;
@@ -638,15 +638,9 @@
   // anywhere.
   moveToTop(Op0, I);
 
-  // Replace the old instruction with a new instruction
-  MBB->remove(I++);
-  unsigned Opcode = MI->getOpcode() == X86::FpUCOM ? X86::FUCOMr : X86::FUCOMIr;
-  I = BuildMI(*MBB, I, Opcode, 1).addReg(getSTReg(Op1));
-
   // If any of the operands are killed by this instruction, free them.
   if (KillsOp0) freeStackSlotAfter(I, Op0);
   if (KillsOp1 && Op0 != Op1) freeStackSlotAfter(I, Op1);
-  delete MI;   // Remove the old instruction
 }
 
 /// handleCondMovFP - Handle two address conditional move instructions.  These
diff --git a/lib/Target/X86/InstSelectSimple.cpp b/lib/Target/X86/InstSelectSimple.cpp
index 1adcd52..7ed3452 100644
--- a/lib/Target/X86/InstSelectSimple.cpp
+++ b/lib/Target/X86/InstSelectSimple.cpp
@@ -1005,11 +1005,11 @@
     break;
   case cFP:
     if (0) { // for processors prior to the P6
-      BuildMI(*MBB, IP, X86::FpUCOM, 2).addReg(Op0r).addReg(Op1r);
+      BuildMI(*MBB, IP, X86::FUCOMr, 2).addReg(Op0r).addReg(Op1r);
       BuildMI(*MBB, IP, X86::FNSTSW8r, 0);
       BuildMI(*MBB, IP, X86::SAHF, 1);
     } else {
-      BuildMI(*MBB, IP, X86::FpUCOMI, 2).addReg(Op0r).addReg(Op1r);
+      BuildMI(*MBB, IP, X86::FUCOMIr, 2).addReg(Op0r).addReg(Op1r);
     }
     break;
 
@@ -1701,11 +1701,11 @@
   case Intrinsic::isnan:
     TmpReg1 = getReg(CI.getOperand(1));
     if (0) { // for processors prior to the P6
-      BuildMI(BB, X86::FpUCOM, 2).addReg(TmpReg1).addReg(TmpReg1);
+      BuildMI(BB, X86::FUCOMr, 2).addReg(TmpReg1).addReg(TmpReg1);
       BuildMI(BB, X86::FNSTSW8r, 0);
       BuildMI(BB, X86::SAHF, 1);
     } else {
-      BuildMI(BB, X86::FpUCOMI, 2).addReg(TmpReg1).addReg(TmpReg1);
+      BuildMI(BB, X86::FUCOMIr, 2).addReg(TmpReg1).addReg(TmpReg1);
     }
     TmpReg2 = getReg(CI);
     BuildMI(BB, X86::SETPr, 0, TmpReg2);
diff --git a/lib/Target/X86/X86FloatingPoint.cpp b/lib/Target/X86/X86FloatingPoint.cpp
index ceb3bf6..ab6d77b 100644
--- a/lib/Target/X86/X86FloatingPoint.cpp
+++ b/lib/Target/X86/X86FloatingPoint.cpp
@@ -614,7 +614,7 @@
   delete MI;   // Remove the old instruction
 }
 
-/// handleCompareFP - Handle FpUCOM and FpUCOMI instructions, which have two FP
+/// handleCompareFP - Handle FUCOM and FUCOMI instructions, which have two FP
 /// register arguments and no explicit destinations.
 /// 
 void FPS::handleCompareFP(MachineBasicBlock::iterator &I) {
@@ -623,7 +623,7 @@
   MachineInstr *MI = I;
 
   unsigned NumOperands = MI->getNumOperands();
-  assert(NumOperands == 2 && "Illegal FpUCOM* instruction!");
+  assert(NumOperands == 2 && "Illegal FUCOM* instruction!");
   unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
   unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1));
   bool KillsOp0 = false, KillsOp1 = false;
@@ -638,15 +638,9 @@
   // anywhere.
   moveToTop(Op0, I);
 
-  // Replace the old instruction with a new instruction
-  MBB->remove(I++);
-  unsigned Opcode = MI->getOpcode() == X86::FpUCOM ? X86::FUCOMr : X86::FUCOMIr;
-  I = BuildMI(*MBB, I, Opcode, 1).addReg(getSTReg(Op1));
-
   // If any of the operands are killed by this instruction, free them.
   if (KillsOp0) freeStackSlotAfter(I, Op0);
   if (KillsOp1 && Op0 != Op1) freeStackSlotAfter(I, Op1);
-  delete MI;   // Remove the old instruction
 }
 
 /// handleCondMovFP - Handle two address conditional move instructions.  These
diff --git a/lib/Target/X86/X86ISelSimple.cpp b/lib/Target/X86/X86ISelSimple.cpp
index 1adcd52..7ed3452 100644
--- a/lib/Target/X86/X86ISelSimple.cpp
+++ b/lib/Target/X86/X86ISelSimple.cpp
@@ -1005,11 +1005,11 @@
     break;
   case cFP:
     if (0) { // for processors prior to the P6
-      BuildMI(*MBB, IP, X86::FpUCOM, 2).addReg(Op0r).addReg(Op1r);
+      BuildMI(*MBB, IP, X86::FUCOMr, 2).addReg(Op0r).addReg(Op1r);
       BuildMI(*MBB, IP, X86::FNSTSW8r, 0);
       BuildMI(*MBB, IP, X86::SAHF, 1);
     } else {
-      BuildMI(*MBB, IP, X86::FpUCOMI, 2).addReg(Op0r).addReg(Op1r);
+      BuildMI(*MBB, IP, X86::FUCOMIr, 2).addReg(Op0r).addReg(Op1r);
     }
     break;
 
@@ -1701,11 +1701,11 @@
   case Intrinsic::isnan:
     TmpReg1 = getReg(CI.getOperand(1));
     if (0) { // for processors prior to the P6
-      BuildMI(BB, X86::FpUCOM, 2).addReg(TmpReg1).addReg(TmpReg1);
+      BuildMI(BB, X86::FUCOMr, 2).addReg(TmpReg1).addReg(TmpReg1);
       BuildMI(BB, X86::FNSTSW8r, 0);
       BuildMI(BB, X86::SAHF, 1);
     } else {
-      BuildMI(BB, X86::FpUCOMI, 2).addReg(TmpReg1).addReg(TmpReg1);
+      BuildMI(BB, X86::FUCOMIr, 2).addReg(TmpReg1).addReg(TmpReg1);
     }
     TmpReg2 = getReg(CI);
     BuildMI(BB, X86::SETPr, 0, TmpReg2);
diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td
index 7de7cb8..e72b8f8 100644
--- a/lib/Target/X86/X86InstrInfo.td
+++ b/lib/Target/X86/X86InstrInfo.td
@@ -863,12 +863,12 @@
 def FDIVRPrST0 : FPrST0PInst<"fdivrp",  0xF0>;   // ST(i) = ST(0) / ST(i), pop
 
 // Floating point compares
-def FUCOMr    : I<"fucom"  , 0xE0, AddRegFrm>, DD, Imp<[ST0],[]>;  // FPSW = compare ST(0) with ST(i)
+def FUCOMr    : FPI<"fucom", 0xE0, AddRegFrm, CompareFP>, DD, Imp<[ST0],[]>;  // FPSW = compare ST(0) with ST(i)
 def FUCOMPr   : I<"fucomp" , 0xE8, AddRegFrm>, DD, Imp<[ST0],[]>;  // FPSW = compare ST(0) with ST(i), pop
 def FUCOMPPr  : I<"fucompp", 0xE9, RawFrm   >, DA, Imp<[ST0],[]>;  // compare ST(0) with ST(1), pop, pop
 
 let printImplicitUsesBefore = 1 in {
-  def FUCOMIr  : I<"fucomi" , 0xE8, AddRegFrm>, DB, Imp<[ST0],[]>;  // CC = compare ST(0) with ST(i)
+  def FUCOMIr  : FPI<"fucomi", 0xE8, AddRegFrm, CompareFP>, DB, Imp<[ST0],[]>;  // CC = compare ST(0) with ST(i)
   def FUCOMIPr : I<"fucomip", 0xE8, AddRegFrm>, DF, Imp<[ST0],[]>;  // CC = compare ST(0) with ST(i), pop
 }
 
diff --git a/lib/Target/X86/X86SimpInstrSelector.cpp b/lib/Target/X86/X86SimpInstrSelector.cpp
index 935f25d..3c02acb 100644
--- a/lib/Target/X86/X86SimpInstrSelector.cpp
+++ b/lib/Target/X86/X86SimpInstrSelector.cpp
@@ -845,7 +845,7 @@
     BuildMI(*MBB, IP, X86::CMP32rr, 2).addReg(Op0r).addReg(Op1r);
     break;
   case cFP:
-    BuildMI(*MBB, IP, X86::FpUCOM, 2).addReg(Op0r).addReg(Op1r);
+    BuildMI(*MBB, IP, X86::FUCOMr, 2).addReg(Op0r).addReg(Op1r);
     BuildMI(*MBB, IP, X86::FNSTSW8r, 0);
     BuildMI(*MBB, IP, X86::SAHF, 1);
     break;