Move code around to prepare for moving some of the logic together to another function
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113267 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index aef02a8..9d507d3 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -5271,9 +5271,6 @@
MachineFunction &MF = DAG.getMachineFunction();
bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize);
- if (isZeroShuffle(SVOp))
- return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
-
// FIXME: this is somehow handled during isel by MMX pattern fragments. Remove
// the check or come up with another solution when all MMX move to intrinsics,
// but don't allow this to be considered legal, we don't want vector_shuffle
@@ -5281,6 +5278,9 @@
if (isMMX && SVOp->isSplat())
return Op;
+ if (isZeroShuffle(SVOp))
+ return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
+
// Promote splats to v4f32.
if (SVOp->isSplat())
return PromoteSplat(SVOp, DAG);