Use new CHECK-DAG support to stabilize CodeGen/PowerPC/recipest.ll
While testing some experimental code to add vector-scalar registers to
PowerPC, I noticed that a couple of independent instructions were
flipped by the scheduler. The new CHECK-DAG support is perfect for
avoiding this problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182020 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/test/CodeGen/PowerPC/recipest.ll b/test/CodeGen/PowerPC/recipest.ll
index 89705fa..38d7682 100644
--- a/test/CodeGen/PowerPC/recipest.ll
+++ b/test/CodeGen/PowerPC/recipest.ll
@@ -14,8 +14,8 @@
ret double %r
; CHECK: @foo
-; CHECK: frsqrte
-; CHECK: fnmsub
+; CHECK-DAG: frsqrte
+; CHECK-DAG: fnmsub
; CHECK: fmul
; CHECK: fmadd
; CHECK: fmul
@@ -39,8 +39,8 @@
ret double %r
; CHECK: @foof
-; CHECK: frsqrtes
-; CHECK: fnmsubs
+; CHECK-DAG: frsqrtes
+; CHECK-DAG: fnmsubs
; CHECK: fmuls
; CHECK: fmadds
; CHECK: fmuls
@@ -61,8 +61,8 @@
ret float %r
; CHECK: @foo
-; CHECK: frsqrte
-; CHECK: fnmsub
+; CHECK-DAG: frsqrte
+; CHECK-DAG: fnmsub
; CHECK: fmul
; CHECK: fmadd
; CHECK: fmul
@@ -86,8 +86,8 @@
ret float %r
; CHECK: @goo
-; CHECK: frsqrtes
-; CHECK: fnmsubs
+; CHECK-DAG: frsqrtes
+; CHECK-DAG: fnmsubs
; CHECK: fmuls
; CHECK: fmadds
; CHECK: fmuls
@@ -120,8 +120,8 @@
ret double %r
; CHECK: @foo2
-; CHECK: fre
-; CHECK: fnmsub
+; CHECK-DAG: fre
+; CHECK-DAG: fnmsub
; CHECK: fmadd
; CHECK: fnmsub
; CHECK: fmadd
@@ -139,8 +139,8 @@
ret float %r
; CHECK: @goo2
-; CHECK: fres
-; CHECK: fnmsubs
+; CHECK-DAG: fres
+; CHECK-DAG: fnmsubs
; CHECK: fmadds
; CHECK: fmuls
; CHECK: blr
@@ -169,8 +169,8 @@
ret double %r
; CHECK: @foo3
-; CHECK: frsqrte
-; CHECK: fnmsub
+; CHECK-DAG: frsqrte
+; CHECK-DAG: fnmsub
; CHECK: fmul
; CHECK: fmadd
; CHECK: fmul
@@ -195,8 +195,8 @@
ret float %r
; CHECK: @goo3
-; CHECK: frsqrtes
-; CHECK: fnmsubs
+; CHECK-DAG: frsqrtes
+; CHECK-DAG: fnmsubs
; CHECK: fmuls
; CHECK: fmadds
; CHECK: fmuls