Remove -post-RA-schedule flag and add a TargetSubtarget method to enable post-register-allocation scheduling. By default it is off. For ARM, enable/disable with -mattr=+/-postrasched. Enable by default for cortex-a8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83122 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/LLVMTargetMachine.cpp b/lib/CodeGen/LLVMTargetMachine.cpp
index 64e28fb..a38d8cc 100644
--- a/lib/CodeGen/LLVMTargetMachine.cpp
+++ b/lib/CodeGen/LLVMTargetMachine.cpp
@@ -45,14 +45,6 @@
cl::desc("Verify generated machine code"),
cl::init(getenv("LLVM_VERIFY_MACHINEINSTRS")!=NULL));
-// This is not enabled by default due to 1) high compile time cost, 2) it's not
-// beneficial to all targets. The plan is to let targets decide whether this
-// is enabled.
-static cl::opt<bool>
-EnablePostRAScheduler("post-RA-scheduler",
- cl::desc("Enable scheduling after register allocation"),
- cl::init(false));
-
// Enable or disable FastISel. Both options are needed, because
// FastISel is enabled by default with -fast, and we wish to be
// able to enable or disable fast-isel independently from -O0.
@@ -326,7 +318,7 @@
printAndVerify(PM);
// Second pass scheduler.
- if (OptLevel != CodeGenOpt::None && EnablePostRAScheduler) {
+ if (OptLevel != CodeGenOpt::None) {
PM.add(createPostRAScheduler());
printAndVerify(PM);
}