Compute feature bits at time of MCSubtargetInfo initialization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134606 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMSubtarget.cpp b/lib/Target/ARM/ARMSubtarget.cpp
index 4affc15..12f12ad 100644
--- a/lib/Target/ARM/ARMSubtarget.cpp
+++ b/lib/Target/ARM/ARMSubtarget.cpp
@@ -38,7 +38,7 @@
ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU,
const std::string &FS)
- : ARMGenSubtargetInfo()
+ : ARMGenSubtargetInfo(TT, CPU, FS)
, ARMProcFamily(Others)
, HasV4TOps(false)
, HasV5TOps(false)
@@ -78,9 +78,6 @@
if (CPUString.empty())
CPUString = "generic";
- if (TT.find("eabi") != std::string::npos)
- TargetABI = ARM_ABI_AAPCS;
-
// Insert the architecture feature derived from the target triple into the
// feature string. This is important for setting features that are implied
// based on the architecture version.
@@ -92,7 +89,7 @@
ArchFS = FS;
}
- ParseSubtargetFeatures(ArchFS, CPUString);
+ ParseSubtargetFeatures(CPUString, ArchFS);
// Thumb2 implies at least V6T2. FIXME: Fix tests to explicitly specify a
// ARM version or CPU and then remove this.
@@ -105,6 +102,9 @@
// After parsing Itineraries, set ItinData.IssueWidth.
computeIssueWidth();
+ if (TT.find("eabi") != std::string::npos)
+ TargetABI = ARM_ABI_AAPCS;
+
if (isAAPCS_ABI())
stackAlignment = 8;
diff --git a/lib/Target/ARM/ARMSubtarget.h b/lib/Target/ARM/ARMSubtarget.h
index 5fad9a7..a199f2b 100644
--- a/lib/Target/ARM/ARMSubtarget.h
+++ b/lib/Target/ARM/ARMSubtarget.h
@@ -25,6 +25,7 @@
namespace llvm {
class GlobalValue;
+class StringRef;
class ARMSubtarget : public ARMGenSubtargetInfo {
protected:
@@ -168,7 +169,7 @@
}
/// ParseSubtargetFeatures - Parses features string setting specified
/// subtarget options. Definition of function is auto generated by tblgen.
- void ParseSubtargetFeatures(const std::string &FS, const std::string &CPU);
+ void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
void computeIssueWidth();
diff --git a/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp b/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
index 2d5c219..402ab4e 100644
--- a/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
+++ b/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
@@ -40,9 +40,10 @@
return X;
}
-MCSubtargetInfo *createARMMCSubtargetInfo() {
+MCSubtargetInfo *createARMMCSubtargetInfo(StringRef TT, StringRef CPU,
+ StringRef FS) {
MCSubtargetInfo *X = new MCSubtargetInfo();
- InitARMMCSubtargetInfo(X);
+ InitARMMCSubtargetInfo(X, CPU, FS);
return X;
}
diff --git a/lib/Target/Alpha/AlphaSubtarget.cpp b/lib/Target/Alpha/AlphaSubtarget.cpp
index fce65fc..000f606 100644
--- a/lib/Target/Alpha/AlphaSubtarget.cpp
+++ b/lib/Target/Alpha/AlphaSubtarget.cpp
@@ -23,13 +23,13 @@
AlphaSubtarget::AlphaSubtarget(const std::string &TT, const std::string &CPU,
const std::string &FS)
- : AlphaGenSubtargetInfo(), HasCT(false) {
+ : AlphaGenSubtargetInfo(TT, CPU, FS), HasCT(false) {
std::string CPUName = CPU;
if (CPUName.empty())
CPUName = "generic";
// Parse features string.
- ParseSubtargetFeatures(FS, CPUName);
+ ParseSubtargetFeatures(CPUName, FS);
// Initialize scheduling itinerary for the specified CPU.
InstrItins = getInstrItineraryForCPU(CPUName);
diff --git a/lib/Target/Alpha/AlphaSubtarget.h b/lib/Target/Alpha/AlphaSubtarget.h
index 847d495..70b3116 100644
--- a/lib/Target/Alpha/AlphaSubtarget.h
+++ b/lib/Target/Alpha/AlphaSubtarget.h
@@ -22,6 +22,7 @@
#include "AlphaGenSubtargetInfo.inc"
namespace llvm {
+class StringRe;
class AlphaSubtarget : public AlphaGenSubtargetInfo {
protected:
@@ -39,7 +40,7 @@
/// ParseSubtargetFeatures - Parses features string setting specified
/// subtarget options. Definition of function is auto generated by tblgen.
- void ParseSubtargetFeatures(const std::string &FS, const std::string &CPU);
+ void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
bool hasCT() const { return HasCT; }
};
diff --git a/lib/Target/Blackfin/BlackfinSubtarget.cpp b/lib/Target/Blackfin/BlackfinSubtarget.cpp
index 9d1d481..696bb87 100644
--- a/lib/Target/Blackfin/BlackfinSubtarget.cpp
+++ b/lib/Target/Blackfin/BlackfinSubtarget.cpp
@@ -23,7 +23,7 @@
BlackfinSubtarget::BlackfinSubtarget(const std::string &TT,
const std::string &CPU,
const std::string &FS)
- : BlackfinGenSubtargetInfo(), sdram(false),
+ : BlackfinGenSubtargetInfo(TT, CPU, FS), sdram(false),
icplb(false),
wa_mi_shift(false),
wa_csync(false),
@@ -39,5 +39,5 @@
if (CPUName.empty())
CPUName = "generic";
// Parse features string.
- ParseSubtargetFeatures(FS, CPUName);
+ ParseSubtargetFeatures(CPUName, FS);
}
diff --git a/lib/Target/Blackfin/BlackfinSubtarget.h b/lib/Target/Blackfin/BlackfinSubtarget.h
index a7d6c16..1a01a81 100644
--- a/lib/Target/Blackfin/BlackfinSubtarget.h
+++ b/lib/Target/Blackfin/BlackfinSubtarget.h
@@ -21,6 +21,7 @@
#include "BlackfinGenSubtargetInfo.inc"
namespace llvm {
+class StringRef;
class BlackfinSubtarget : public BlackfinGenSubtargetInfo {
bool sdram;
@@ -40,8 +41,7 @@
/// ParseSubtargetFeatures - Parses features string setting specified
/// subtarget options. Definition of function is auto generated by tblgen.
- void ParseSubtargetFeatures(const std::string &FS,
- const std::string &CPU);
+ void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
};
} // end namespace llvm
diff --git a/lib/Target/CellSPU/SPUSubtarget.cpp b/lib/Target/CellSPU/SPUSubtarget.cpp
index 2481e3b..cb94d28 100644
--- a/lib/Target/CellSPU/SPUSubtarget.cpp
+++ b/lib/Target/CellSPU/SPUSubtarget.cpp
@@ -25,7 +25,7 @@
SPUSubtarget::SPUSubtarget(const std::string &TT, const std::string &CPU,
const std::string &FS) :
- SPUGenSubtargetInfo(),
+ SPUGenSubtargetInfo(TT, CPU, FS),
StackAlignment(16),
ProcDirective(SPU::DEFAULT_PROC),
UseLargeMem(false)
@@ -35,7 +35,7 @@
std::string default_cpu("v0");
// Parse features string.
- ParseSubtargetFeatures(FS, default_cpu);
+ ParseSubtargetFeatures(default_cpu, FS);
// Initialize scheduling itinerary for the specified CPU.
InstrItins = getInstrItineraryForCPU(default_cpu);
diff --git a/lib/Target/CellSPU/SPUSubtarget.h b/lib/Target/CellSPU/SPUSubtarget.h
index 19b97d3..7c4aa14 100644
--- a/lib/Target/CellSPU/SPUSubtarget.h
+++ b/lib/Target/CellSPU/SPUSubtarget.h
@@ -23,6 +23,7 @@
namespace llvm {
class GlobalValue;
+ class StringRef;
namespace SPU {
enum {
@@ -57,7 +58,7 @@
/// ParseSubtargetFeatures - Parses features string setting specified
/// subtarget options. Definition of function is auto generated by tblgen.
- void ParseSubtargetFeatures(const std::string &FS, const std::string &CPU);
+ void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
/// SetJITMode - This is called to inform the subtarget info that we are
/// producing code for the JIT.
diff --git a/lib/Target/MBlaze/MBlazeSubtarget.cpp b/lib/Target/MBlaze/MBlazeSubtarget.cpp
index 81578ce..8e706cd 100644
--- a/lib/Target/MBlaze/MBlazeSubtarget.cpp
+++ b/lib/Target/MBlaze/MBlazeSubtarget.cpp
@@ -26,7 +26,7 @@
MBlazeSubtarget::MBlazeSubtarget(const std::string &TT,
const std::string &CPU,
const std::string &FS):
- MBlazeGenSubtargetInfo(),
+ MBlazeGenSubtargetInfo(TT, CPU, FS),
HasBarrel(false), HasDiv(false), HasMul(false), HasPatCmp(false),
HasFPU(false), HasMul64(false), HasSqrt(false)
{
@@ -34,7 +34,7 @@
std::string CPUName = CPU;
if (CPUName.empty())
CPUName = "mblaze";
- ParseSubtargetFeatures(FS, CPUName);
+ ParseSubtargetFeatures(CPUName, FS);
// Only use instruction scheduling if the selected CPU has an instruction
// itinerary (the default CPU is the only one that doesn't).
diff --git a/lib/Target/MBlaze/MBlazeSubtarget.h b/lib/Target/MBlaze/MBlazeSubtarget.h
index 7d70040..43b0197 100644
--- a/lib/Target/MBlaze/MBlazeSubtarget.h
+++ b/lib/Target/MBlaze/MBlazeSubtarget.h
@@ -22,6 +22,7 @@
#include "MBlazeGenSubtargetInfo.inc"
namespace llvm {
+class StringRef;
class MBlazeSubtarget : public MBlazeGenSubtargetInfo {
@@ -46,7 +47,7 @@
/// ParseSubtargetFeatures - Parses features string setting specified
/// subtarget options. Definition of function is auto generated by tblgen.
- void ParseSubtargetFeatures(const std::string &FS, const std::string &CPU);
+ void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
/// Compute the number of maximum number of issues per cycle for the
/// MBlaze scheduling itineraries.
diff --git a/lib/Target/MSP430/MSP430Subtarget.cpp b/lib/Target/MSP430/MSP430Subtarget.cpp
index bd8d7cd..42cc882 100644
--- a/lib/Target/MSP430/MSP430Subtarget.cpp
+++ b/lib/Target/MSP430/MSP430Subtarget.cpp
@@ -22,10 +22,11 @@
using namespace llvm;
MSP430Subtarget::MSP430Subtarget(const std::string &TT,
- const std::string &CPUIgnored,
- const std::string &FS) {
- std::string CPU = "generic";
+ const std::string &CPU,
+ const std::string &FS) :
+ MSP430GenSubtargetInfo(TT, CPU, FS) {
+ std::string CPUName = "generic";
// Parse features string.
- ParseSubtargetFeatures(FS, CPU);
+ ParseSubtargetFeatures(CPUName, FS);
}
diff --git a/lib/Target/MSP430/MSP430Subtarget.h b/lib/Target/MSP430/MSP430Subtarget.h
index ead213b..1ce5f11 100644
--- a/lib/Target/MSP430/MSP430Subtarget.h
+++ b/lib/Target/MSP430/MSP430Subtarget.h
@@ -22,6 +22,7 @@
#include <string>
namespace llvm {
+class StringRef;
class MSP430Subtarget : public MSP430GenSubtargetInfo {
bool ExtendedInsts;
@@ -34,7 +35,7 @@
/// ParseSubtargetFeatures - Parses features string setting specified
/// subtarget options. Definition of function is auto generated by tblgen.
- void ParseSubtargetFeatures(const std::string &FS, const std::string &CPU);
+ void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
};
} // End llvm namespace
diff --git a/lib/Target/Mips/MipsSubtarget.cpp b/lib/Target/Mips/MipsSubtarget.cpp
index a96f872..7a5d417 100644
--- a/lib/Target/Mips/MipsSubtarget.cpp
+++ b/lib/Target/Mips/MipsSubtarget.cpp
@@ -23,7 +23,7 @@
MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU,
const std::string &FS, bool little) :
- MipsGenSubtargetInfo(),
+ MipsGenSubtargetInfo(TT, CPU, FS),
MipsArchVersion(Mips1), MipsABI(O32), IsLittle(little), IsSingleFloat(false),
IsFP64bit(false), IsGP64bit(false), HasVFPU(false), IsLinux(true),
HasSEInReg(false), HasCondMov(false), HasMulDivAdd(false), HasMinMax(false),
@@ -35,7 +35,7 @@
MipsArchVersion = Mips1;
// Parse features string.
- ParseSubtargetFeatures(FS, CPUName);
+ ParseSubtargetFeatures(CPUName, FS);
// Initialize scheduling itinerary for the specified CPU.
InstrItins = getInstrItineraryForCPU(CPUName);
diff --git a/lib/Target/Mips/MipsSubtarget.h b/lib/Target/Mips/MipsSubtarget.h
index ae76470..533d4af 100644
--- a/lib/Target/Mips/MipsSubtarget.h
+++ b/lib/Target/Mips/MipsSubtarget.h
@@ -22,6 +22,7 @@
#include "MipsGenSubtargetInfo.inc"
namespace llvm {
+class StringRef;
class MipsSubtarget : public MipsGenSubtargetInfo {
@@ -99,7 +100,7 @@
/// ParseSubtargetFeatures - Parses features string setting specified
/// subtarget options. Definition of function is auto generated by tblgen.
- void ParseSubtargetFeatures(const std::string &FS, const std::string &CPU);
+ void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
bool isMips1() const { return MipsArchVersion == Mips1; }
bool isMips32() const { return MipsArchVersion >= Mips32; }
diff --git a/lib/Target/PTX/PTXSubtarget.cpp b/lib/Target/PTX/PTXSubtarget.cpp
index 5eff24a..846eee1 100644
--- a/lib/Target/PTX/PTXSubtarget.cpp
+++ b/lib/Target/PTX/PTXSubtarget.cpp
@@ -23,7 +23,7 @@
PTXSubtarget::PTXSubtarget(const std::string &TT, const std::string &CPU,
const std::string &FS, bool is64Bit)
- : PTXGenSubtargetInfo(),
+ : PTXGenSubtargetInfo(TT, CPU, FS),
PTXTarget(PTX_COMPUTE_1_0),
PTXVersion(PTX_VERSION_2_0),
SupportsDouble(false),
@@ -32,7 +32,7 @@
std::string TARGET = CPU;
if (TARGET.empty())
TARGET = "generic";
- ParseSubtargetFeatures(FS, TARGET);
+ ParseSubtargetFeatures(TARGET, FS);
}
std::string PTXSubtarget::getTargetString() const {
diff --git a/lib/Target/PTX/PTXSubtarget.h b/lib/Target/PTX/PTXSubtarget.h
index 913f0a2..0921f1f 100644
--- a/lib/Target/PTX/PTXSubtarget.h
+++ b/lib/Target/PTX/PTXSubtarget.h
@@ -20,6 +20,8 @@
#include "PTXGenSubtargetInfo.inc"
namespace llvm {
+class StringRef;
+
class PTXSubtarget : public PTXGenSubtargetInfo {
public:
@@ -112,8 +114,7 @@
(PTXTarget >= PTX_COMPUTE_2_0 && PTXTarget < PTX_LAST_COMPUTE);
}
- void ParseSubtargetFeatures(const std::string &FS,
- const std::string &CPU);
+ void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
}; // class PTXSubtarget
} // namespace llvm
diff --git a/lib/Target/PowerPC/PPCSubtarget.cpp b/lib/Target/PowerPC/PPCSubtarget.cpp
index 75ee1c0..7eeeaf5 100644
--- a/lib/Target/PowerPC/PPCSubtarget.cpp
+++ b/lib/Target/PowerPC/PPCSubtarget.cpp
@@ -64,7 +64,7 @@
PPCSubtarget::PPCSubtarget(const std::string &TT, const std::string &CPU,
const std::string &FS, bool is64Bit)
- : PPCGenSubtargetInfo()
+ : PPCGenSubtargetInfo(TT, CPU, FS)
, StackAlignment(16)
, DarwinDirective(PPC::DIR_NONE)
, IsGigaProcessor(false)
@@ -88,7 +88,7 @@
#endif
// Parse features string.
- ParseSubtargetFeatures(FS, CPUName);
+ ParseSubtargetFeatures(CPUName, FS);
// Initialize scheduling itinerary for the specified CPU.
InstrItins = getInstrItineraryForCPU(CPUName);
diff --git a/lib/Target/PowerPC/PPCSubtarget.h b/lib/Target/PowerPC/PPCSubtarget.h
index c89f922..e028de6 100644
--- a/lib/Target/PowerPC/PPCSubtarget.h
+++ b/lib/Target/PowerPC/PPCSubtarget.h
@@ -26,6 +26,7 @@
#undef PPC
namespace llvm {
+class StringRef;
namespace PPC {
// -m directive values.
@@ -80,8 +81,7 @@
/// ParseSubtargetFeatures - Parses features string setting specified
/// subtarget options. Definition of function is auto generated by tblgen.
- void ParseSubtargetFeatures(const std::string &FS, const std::string &CPU);
-
+ void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
/// SetJITMode - This is called to inform the subtarget info that we are
/// producing code for the JIT.
diff --git a/lib/Target/Sparc/SparcSubtarget.cpp b/lib/Target/Sparc/SparcSubtarget.cpp
index ee3cc03..c8281ce 100644
--- a/lib/Target/Sparc/SparcSubtarget.cpp
+++ b/lib/Target/Sparc/SparcSubtarget.cpp
@@ -22,7 +22,7 @@
SparcSubtarget::SparcSubtarget(const std::string &TT, const std::string &CPU,
const std::string &FS, bool is64Bit) :
- SparcGenSubtargetInfo(),
+ SparcGenSubtargetInfo(TT, CPU, FS),
IsV9(false),
V8DeprecatedInsts(false),
IsVIS(false),
@@ -39,5 +39,5 @@
IsV9 = CPUName == "v9";
// Parse features string.
- ParseSubtargetFeatures(FS, CPUName);
+ ParseSubtargetFeatures(CPUName, FS);
}
diff --git a/lib/Target/Sparc/SparcSubtarget.h b/lib/Target/Sparc/SparcSubtarget.h
index 257f22a..00a04c3 100644
--- a/lib/Target/Sparc/SparcSubtarget.h
+++ b/lib/Target/Sparc/SparcSubtarget.h
@@ -21,6 +21,7 @@
#include "SparcGenSubtargetInfo.inc"
namespace llvm {
+class StringRef;
class SparcSubtarget : public SparcGenSubtargetInfo {
bool IsV9;
@@ -38,7 +39,7 @@
/// ParseSubtargetFeatures - Parses features string setting specified
/// subtarget options. Definition of function is auto generated by tblgen.
- void ParseSubtargetFeatures(const std::string &FS, const std::string &CPU);
+ void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
bool is64Bit() const { return Is64Bit; }
std::string getDataLayout() const {
diff --git a/lib/Target/SystemZ/SystemZSubtarget.cpp b/lib/Target/SystemZ/SystemZSubtarget.cpp
index 4388109..518c09f 100644
--- a/lib/Target/SystemZ/SystemZSubtarget.cpp
+++ b/lib/Target/SystemZ/SystemZSubtarget.cpp
@@ -26,13 +26,13 @@
SystemZSubtarget::SystemZSubtarget(const std::string &TT,
const std::string &CPU,
const std::string &FS):
- SystemZGenSubtargetInfo(), HasZ10Insts(false) {
+ SystemZGenSubtargetInfo(TT, CPU, FS), HasZ10Insts(false) {
std::string CPUName = CPU;
if (CPUName.empty())
CPUName = "z9";
// Parse features string.
- ParseSubtargetFeatures(FS, CPUName);
+ ParseSubtargetFeatures(CPUName, FS);
}
/// True if accessing the GV requires an extra load.
diff --git a/lib/Target/SystemZ/SystemZSubtarget.h b/lib/Target/SystemZ/SystemZSubtarget.h
index 6ac606a..55cfd80 100644
--- a/lib/Target/SystemZ/SystemZSubtarget.h
+++ b/lib/Target/SystemZ/SystemZSubtarget.h
@@ -22,6 +22,7 @@
namespace llvm {
class GlobalValue;
+class StringRef;
class TargetMachine;
class SystemZSubtarget : public SystemZGenSubtargetInfo {
@@ -35,7 +36,7 @@
/// ParseSubtargetFeatures - Parses features string setting specified
/// subtarget options. Definition of function is auto generated by tblgen.
- void ParseSubtargetFeatures(const std::string &FS, const std::string &CPU);
+ void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
bool isZ10() const { return HasZ10Insts; }
diff --git a/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp b/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
index f24c356..0f6b579 100644
--- a/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
+++ b/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
@@ -40,9 +40,10 @@
return X;
}
-MCSubtargetInfo *createX86MCSubtargetInfo() {
+MCSubtargetInfo *createX86MCSubtargetInfo(StringRef TT, StringRef CPU,
+ StringRef FS) {
MCSubtargetInfo *X = new MCSubtargetInfo();
- InitX86MCSubtargetInfo(X);
+ InitX86MCSubtargetInfo(X, CPU, FS);
return X;
}
diff --git a/lib/Target/X86/X86Subtarget.cpp b/lib/Target/X86/X86Subtarget.cpp
index a1e6d7b..1c1a10d 100644
--- a/lib/Target/X86/X86Subtarget.cpp
+++ b/lib/Target/X86/X86Subtarget.cpp
@@ -292,7 +292,7 @@
X86Subtarget::X86Subtarget(const std::string &TT, const std::string &CPU,
const std::string &FS,
bool is64Bit, unsigned StackAlignOverride)
- : X86GenSubtargetInfo()
+ : X86GenSubtargetInfo(TT, CPU, FS)
, PICStyle(PICStyles::None)
, X86SSELevel(NoMMXSSE)
, X863DNowLevel(NoThreeDNow)
@@ -320,7 +320,7 @@
std::string CPUName = CPU;
if (CPUName.empty())
CPUName = sys::getHostCPUName();
- ParseSubtargetFeatures(FS, CPUName);
+ ParseSubtargetFeatures(CPUName, FS);
// All X86-64 CPUs also have SSE2, however user might request no SSE via
// -mattr, so don't force SSELevel here.
if (HasAVX)
diff --git a/lib/Target/X86/X86Subtarget.h b/lib/Target/X86/X86Subtarget.h
index d49b871..f6250b6 100644
--- a/lib/Target/X86/X86Subtarget.h
+++ b/lib/Target/X86/X86Subtarget.h
@@ -24,6 +24,7 @@
namespace llvm {
class GlobalValue;
+class StringRef;
class TargetMachine;
/// PICStyles - The X86 backend supports a number of different styles of PIC.
@@ -135,7 +136,7 @@
/// ParseSubtargetFeatures - Parses features string setting specified
/// subtarget options. Definition of function is auto generated by tblgen.
- void ParseSubtargetFeatures(const std::string &FS, const std::string &CPU);
+ void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
/// AutoDetectSubtargetFeatures - Auto-detect CPU features using CPUID
/// instruction.
diff --git a/lib/Target/XCore/XCoreSubtarget.cpp b/lib/Target/XCore/XCoreSubtarget.cpp
index 6485c4e..c727183 100644
--- a/lib/Target/XCore/XCoreSubtarget.cpp
+++ b/lib/Target/XCore/XCoreSubtarget.cpp
@@ -23,6 +23,6 @@
XCoreSubtarget::XCoreSubtarget(const std::string &TT,
const std::string &CPU, const std::string &FS)
- : XCoreGenSubtargetInfo()
+ : XCoreGenSubtargetInfo(TT, CPU, FS)
{
}
diff --git a/lib/Target/XCore/XCoreSubtarget.h b/lib/Target/XCore/XCoreSubtarget.h
index 2e52571..7b29fa2 100644
--- a/lib/Target/XCore/XCoreSubtarget.h
+++ b/lib/Target/XCore/XCoreSubtarget.h
@@ -22,6 +22,7 @@
#include "XCoreGenSubtargetInfo.inc"
namespace llvm {
+class StringRef;
class XCoreSubtarget : public XCoreGenSubtargetInfo {
@@ -34,7 +35,7 @@
/// ParseSubtargetFeatures - Parses features string setting specified
/// subtarget options. Definition of function is auto generated by tblgen.
- void ParseSubtargetFeatures(const std::string &FS, const std::string &CPU);
+ void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
};
} // End llvm namespace