Push processor descriptions to the top of target and add command line info.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23820 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/Target.td b/lib/Target/Target.td
index 4e36223..994a71d 100644
--- a/lib/Target/Target.td
+++ b/lib/Target/Target.td
@@ -242,6 +242,45 @@
}
//===----------------------------------------------------------------------===//
+// Pull in the common support for scheduling
+//
+include "../TargetSchedule.td"
+
+//===----------------------------------------------------------------------===//
+// SubtargetFeature - A characteristic of the chip set.
+//
+class SubtargetFeature<string n, string d> {
+ // Name - Feature name. Used by command line (-mattr=) to determine the
+ // appropriate target chip.
+ //
+ string Name = n;
+
+ // Desc - Feature description. Used by command line (-mattr=) to display help
+ // information.
+ //
+ string Desc = d;
+}
+
+//===----------------------------------------------------------------------===//
+// Processor chip sets - These values represent each of the chip sets supported
+// by the scheduler. Each Processor definition requires corresponding
+// instruction itineraries.
+//
+class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> {
+ // Name - Chip set name. Used by command line (-mcpu=) to determine the
+ // appropriate target chip.
+ //
+ string Name = n;
+
+ // ProcItin - The scheduling information for the target processor.
+ //
+ ProcessorItineraries ProcItin = pi;
+
+ // Features - list of
+ list<SubtargetFeature> Features;
+}
+
+//===----------------------------------------------------------------------===//
// Pull in the common support for DAG isel generation
//
include "../TargetSelectionDAG.td"