commit 0e4dd01ffc44222d68c3c5e2c1a45c8c1a1d20ae
author Andrew Lenharth <andrewl@lenharth.org> Tue Jun 13 18:27:39 2006 +0000
committer Andrew Lenharth <andrewl@lenharth.org> Tue Jun 13 18:27:39 2006 +0000
tree 3a7623fb6c5e4473c79f5b8ee92ebd8d46f5c2d7
parent c4fa603347e798c94f54430227df8265736ef183

It really helps to be returning to the correct place


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28769 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/Alpha/AlphaISelLowering.cpp

diff --git a/lib/Target/Alpha/AlphaISelLowering.cpp b/lib/Target/Alpha/AlphaISelLowering.cpp
index 3a5c7d9..fda3096 100644
--- a/lib/Target/Alpha/AlphaISelLowering.cpp
+++ b/lib/Target/Alpha/AlphaISelLowering.cpp
@@ -154,6 +154,7 @@
   case AlphaISD::GPRelLo: return "Alpha::GPRelLo";
   case AlphaISD::RelLit: return "Alpha::RelLit";
   case AlphaISD::GlobalBaseReg: return "Alpha::GlobalBaseReg";
+  case AlphaISD::GlobalRetAddr: return "Alpha::GlobalRetAddr";
   case AlphaISD::CALL:   return "Alpha::CALL";
   case AlphaISD::DivCall: return "Alpha::DivCall";
   case AlphaISD::RET_FLAG: return "Alpha::RET_FLAG";
@@ -268,14 +269,17 @@
   return DAG.getNode(ISD::MERGE_VALUES, RetVT, ArgValues);
 }
 
-static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
-  SDOperand Copy;
+static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG, unsigned int RA) {
+  SDOperand Copy = DAG.getCopyToReg(Op.getOperand(0), Alpha::R26, 
+				    DAG.getNode(AlphaISD::GlobalRetAddr, MVT::i64),
+				    SDOperand());
   switch (Op.getNumOperands()) {
   default:
     assert(0 && "Do not know how to return this many arguments!");
     abort();
   case 1: 
-    return SDOperand(); // ret void is legal
+    break;
+    //return SDOperand(); // ret void is legal
   case 3: {
     MVT::ValueType ArgVT = Op.getOperand(1).getValueType();
     unsigned ArgReg;
@@ -285,8 +289,7 @@
       assert(MVT::isFloatingPoint(ArgVT));
       ArgReg = Alpha::F0;
     }
-    Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1),
-                            SDOperand());
+    Copy = DAG.getCopyToReg(Copy, ArgReg, Op.getOperand(1), Copy.getValue(1));
     if(DAG.getMachineFunction().liveout_empty())
       DAG.getMachineFunction().addLiveOut(ArgReg);
     break;
@@ -384,7 +387,7 @@
 							   VarArgsBase,
 							   VarArgsOffset,
 							   GP, RA);
-  case ISD::RET: return LowerRET(Op,DAG);
+  case ISD::RET: return LowerRET(Op,DAG, getVRegRA());
   case ISD::SINT_TO_FP: {
     assert(MVT::i64 == Op.getOperand(0).getValueType() && 
            "Unhandled SINT_TO_FP type in custom expander!");