commit 0eb61037f7f554f705a511b47a6cf43f0b39bb9a
author Brian Gaeke <gaeke@uiuc.edu> Mon Apr 19 19:12:12 2004 +0000
committer Brian Gaeke <gaeke@uiuc.edu> Mon Apr 19 19:12:12 2004 +0000
tree f6770c2a377b5860bd5b5971466257c750cf7bf3
parent 9a459abed2ecd06b5b5d2f517b27cd9bf1919690

Make it legal to request a load or store of %fsr.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@13073 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/SparcV9/SparcV9RegInfo.cpp

diff --git a/lib/Target/SparcV9/SparcV9RegInfo.cpp b/lib/Target/SparcV9/SparcV9RegInfo.cpp
index b6da2e6..0f59848 100644
--- a/lib/Target/SparcV9/SparcV9RegInfo.cpp
+++ b/lib/Target/SparcV9/SparcV9RegInfo.cpp
@@ -808,6 +808,7 @@
     cpReg2MemMI(mvec, scratchReg, PtrReg, Offset, IntRegType);
     return;
 
+  case SpecialRegType: // used only for %fsr itself.
   case FloatCCRegType: {
     unsigned fsrReg =  getUnifiedRegNum(SparcV9RegInfo::SpecialRegClassID,
                                            SparcV9SpecialRegClass::fsr);
@@ -898,6 +899,7 @@
                                     SparcV9IntCCRegClass::ccr), MachineOperand::Def));
     break;
     
+  case SpecialRegType: // used only for %fsr itself
   case FloatCCRegType: {
     unsigned fsrRegNum =  getUnifiedRegNum(SparcV9RegInfo::SpecialRegClassID,
                                            SparcV9SpecialRegClass::fsr);