Make X86::FsFLD0SS / FsFLD0SD real pseudo-instructions.
Like V_SET0, these instructions are expanded by ExpandPostRA to xorps /
vxorps so they can participate in execution domain swizzling.
This also makes the AVX variants redundant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145440 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/test/CodeGen/X86/fast-isel-x86-64.ll b/test/CodeGen/X86/fast-isel-x86-64.ll
index 377fd11..d8f4663 100644
--- a/test/CodeGen/X86/fast-isel-x86-64.ll
+++ b/test/CodeGen/X86/fast-isel-x86-64.ll
@@ -225,18 +225,20 @@
; CHECK-NEXT: je
}
-; Check that 0.0 is materialized using pxor
+; Check that 0.0 is materialized using xorps
define void @test18(float* %p1) {
store float 0.0, float* %p1
ret void
; CHECK: test18:
-; CHECK: pxor
+; CHECK: xorps
}
+
+; Without any type hints, doubles use the smaller xorps instead of xorpd.
define void @test19(double* %p1) {
store double 0.0, double* %p1
ret void
; CHECK: test19:
-; CHECK: pxor
+; CHECK: xorps
}
; Check that we fast-isel sret
@@ -252,12 +254,12 @@
}
declare void @test20sret(%struct.a* sret)
-; Check that -0.0 is not materialized using pxor
+; Check that -0.0 is not materialized using xor
define void @test21(double* %p1) {
store double -0.0, double* %p1
ret void
; CHECK: test21:
-; CHECK-NOT: pxor
+; CHECK-NOT: xor
; CHECK: movsd LCPI
}