X86_COND_C and X86_COND_NC are alternate mnemonics for
X86_COND_B and X86_COND_AE, respectively.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61835 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/X86/X86FastISel.cpp b/lib/Target/X86/X86FastISel.cpp
index 3056e39..2cb05e2 100644
--- a/lib/Target/X86/X86FastISel.cpp
+++ b/lib/Target/X86/X86FastISel.cpp
@@ -758,11 +758,11 @@
// %obit = extractvalue { i32, i1 } %t, 1
// br i1 %obit, label %overflow, label %normal
//
- // The %sum and %obit are converted in an ADD and a SETO/SETC before
+ // The %sum and %obit are converted in an ADD and a SETO/SETB before
// reaching the branch. Therefore, we search backwards through the MBB
- // looking for the SETO/SETC instruction. If an instruction modifies the
- // EFLAGS register before we reach the SETO/SETC instruction, then we can't
- // convert the branch into a JO/JC instruction.
+ // looking for the SETO/SETB instruction. If an instruction modifies the
+ // EFLAGS register before we reach the SETO/SETB instruction, then we can't
+ // convert the branch into a JO/JB instruction.
Value *Agg = EI->getAggregateOperand();
@@ -814,9 +814,9 @@
if (SetMI) {
unsigned OpCode = SetMI->getOpcode();
- if (OpCode == X86::SETOr || OpCode == X86::SETCr) {
+ if (OpCode == X86::SETOr || OpCode == X86::SETBr) {
BuildMI(MBB, TII.get((OpCode == X86::SETOr) ?
- X86::JO : X86::JC)).addMBB(TrueMBB);
+ X86::JO : X86::JB)).addMBB(TrueMBB);
FastEmitBranch(FalseMBB);
MBB->addSuccessor(TrueMBB);
return true;
@@ -1086,7 +1086,7 @@
ResultReg = createResultReg(TLI.getRegClassFor(MVT::i8));
BuildMI(MBB, TII.get((Intrinsic == Intrinsic::sadd_with_overflow) ?
- X86::SETOr : X86::SETCr), ResultReg);
+ X86::SETOr : X86::SETBr), ResultReg);
return true;
}
}