X86_COND_C and X86_COND_NC are alternate mnemonics for
X86_COND_B and X86_COND_AE, respectively.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61835 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index c282f91..eda29f0 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -5057,7 +5057,7 @@
RHS = DAG.getNode(ISD::ANY_EXTEND, LHS.getValueType(), RHS);
SDValue BT = DAG.getNode(X86ISD::BT, MVT::i32, LHS, RHS);
- unsigned Cond = CC == ISD::SETEQ ? X86::COND_NC : X86::COND_C;
+ unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
return DAG.getNode(X86ISD::SETCC, MVT::i8,
DAG.getConstant(Cond, MVT::i8), BT);
}
@@ -5283,7 +5283,7 @@
switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
default: break;
case X86::COND_O:
- case X86::COND_C:
+ case X86::COND_B:
// These can only come from an arithmetic instruction with overflow,
// e.g. SADDO, UADDO.
Cond = Cond.getNode()->getOperand(1);
@@ -6243,7 +6243,7 @@
break;
case ISD::UADDO:
BaseOp = X86ISD::ADD;
- Cond = X86::COND_C;
+ Cond = X86::COND_B;
break;
case ISD::SSUBO:
BaseOp = X86ISD::SUB;
@@ -6251,7 +6251,7 @@
break;
case ISD::USUBO:
BaseOp = X86ISD::SUB;
- Cond = X86::COND_C;
+ Cond = X86::COND_B;
break;
case ISD::SMULO:
BaseOp = X86ISD::SMUL;
@@ -6259,7 +6259,7 @@
break;
case ISD::UMULO:
BaseOp = X86ISD::UMUL;
- Cond = X86::COND_C;
+ Cond = X86::COND_B;
break;
}