commit 10b400705dcdef25754b3c3c765c40c6513df1b1
author Andrew Lenharth <andrewl@lenharth.org> Thu Jan 27 07:58:15 2005 +0000
committer Andrew Lenharth <andrewl@lenharth.org> Thu Jan 27 07:58:15 2005 +0000
tree 53a086e8ef55800ec00d7cce6e30346ac187970d
parent d2bb960d8cc1c76ddb2c5be400b9c25bbfa6c501

Floating point instructions like Floating point registers


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19856 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/Alpha/AlphaISelPattern.cpp

diff --git a/lib/Target/Alpha/AlphaISelPattern.cpp b/lib/Target/Alpha/AlphaISelPattern.cpp
index b9abf46..bae321e 100644
--- a/lib/Target/Alpha/AlphaISelPattern.cpp
+++ b/lib/Target/Alpha/AlphaISelPattern.cpp
@@ -333,7 +333,7 @@
     if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N)) {
       if (CN->isExactlyValue(+0.0) ||
           CN->isExactlyValue(-0.0)) {
-        BuildMI(BB, Alpha::CPYS, 2, Result).addReg(R31).addReg(R31);
+        BuildMI(BB, Alpha::CPYS, 2, Result).addReg(Alpha::F31).addReg(Alpha::F31);
       } else {
         abort();
       }