commit 11cefd926a1be9e6cd52b4e189a99081a385d57f
author Nate Begeman <natebegeman@mac.com> Sat Jul 16 02:00:20 2005 +0000
committer Nate Begeman <natebegeman@mac.com> Sat Jul 16 02:00:20 2005 +0000
tree 7bbdcdef8d0a951ebbd1cb4781e7a40c12cea64e
parent 9035b99abf36be73ef26a4d31f67a2b4d5d74e99

Teach the register allocator that movaps is also a move instruction


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22451 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/X86/X86InstrInfo.cpp

diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp
index 957360b..2fec723 100644
--- a/lib/Target/X86/X86InstrInfo.cpp
+++ b/lib/Target/X86/X86InstrInfo.cpp
@@ -28,7 +28,7 @@
                                unsigned& destReg) const {
   MachineOpCode oc = MI.getOpcode();
   if (oc == X86::MOV8rr || oc == X86::MOV16rr || oc == X86::MOV32rr ||
-      oc == X86::FpMOV  || oc == X86::MOVAPDrr) {
+      oc == X86::FpMOV  || oc == X86::MOVAPDrr || oc == X86::MOVAPSrr) {
       assert(MI.getNumOperands() == 2 &&
              MI.getOperand(0).isRegister() &&
              MI.getOperand(1).isRegister() &&