| commit | 11db068721d44fd5f9b0c2a3a4c90f813d2eae9c | [log] [tgz] |
|---|---|---|
| author | Evan Cheng <evan.cheng@apple.com> | Wed Aug 11 06:22:01 2010 +0000 |
| committer | Evan Cheng <evan.cheng@apple.com> | Wed Aug 11 06:22:01 2010 +0000 |
| tree | 7649fa37f8869eb5f872a3d73eb58587295b6cf1 | |
| parent | 3483acabf012b847b13b969ebd9ce5c4d16d9eb7 [diff] |
- Add subtarget feature -mattr=+db which determine whether an ARM cpu has the memory and synchronization barrier dmb and dsb instructions. - Change instruction names to something more sensible (matching name of actual instructions). - Added tests for memory barrier codegen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110785 91177308-0d34-0410-b5e6-96231b3b80d8