diff --git a/lib/CodeGen/InstrSched/SchedGraph.cpp b/lib/CodeGen/InstrSched/SchedGraph.cpp
index 4bcdf47..4b4adc9 100644
--- a/lib/CodeGen/InstrSched/SchedGraph.cpp
+++ b/lib/CodeGen/InstrSched/SchedGraph.cpp
@@ -623,31 +623,30 @@
 
 
 void
-SchedGraph::addEdgesForInstruction(const MachineInstr& minstr,
+SchedGraph::addEdgesForInstruction(const MachineInstr& MI,
                                    const ValueToDefVecMap& valueToDefVecMap,
 				   const TargetMachine& target)
 {
-  SchedGraphNode* node = this->getGraphNodeForInstr(&minstr);
+  SchedGraphNode* node = getGraphNodeForInstr(&MI);
   if (node == NULL)
     return;
   
   // Add edges for all operands of the machine instruction.
   // 
-  for (unsigned i=0, numOps=minstr.getNumOperands(); i < numOps; i++)
+  for (unsigned i = 0, numOps = MI.getNumOperands(); i != numOps; ++i)
     {
-      const MachineOperand& mop = minstr.getOperand(i);
-      switch(mop.getOperandType())
+      switch (MI.getOperandType(i))
 	{
 	case MachineOperand::MO_VirtualRegister:
 	case MachineOperand::MO_CCRegister:
 	  if (const Instruction* srcI =
-              dyn_cast_or_null<Instruction>(mop.getVRegValue()))
+              dyn_cast_or_null<Instruction>(MI.getOperand(i).getVRegValue()))
             {
               ValueToDefVecMap::const_iterator I = valueToDefVecMap.find(srcI);
               if (I != valueToDefVecMap.end())
-                addEdgesForValue(node, (*I).second, mop.getVRegValue(),
-                                 minstr.operandIsDefined(i),
-                                 minstr.operandIsDefinedAndUsed(i), target);
+                addEdgesForValue(node, I->second, srcI,
+                                 MI.operandIsDefined(i),
+                                 MI.operandIsDefinedAndUsed(i), target);
             }
 	  break;
 	  
@@ -669,17 +668,17 @@
   // Examples include function arguments to a Call instructions or the return
   // value of a Ret instruction.
   // 
-  for (unsigned i=0, N=minstr.getNumImplicitRefs(); i < N; ++i)
-    if (! minstr.implicitRefIsDefined(i) ||
-        minstr.implicitRefIsDefinedAndUsed(i))
-      if (const Instruction* srcI =
-          dyn_cast_or_null<Instruction>(minstr.getImplicitRef(i)))
+  for (unsigned i=0, N=MI.getNumImplicitRefs(); i < N; ++i)
+    if (! MI.implicitRefIsDefined(i) ||
+        MI.implicitRefIsDefinedAndUsed(i))
+      if (const Instruction *srcI =
+          dyn_cast_or_null<Instruction>(MI.getImplicitRef(i)))
         {
           ValueToDefVecMap::const_iterator I = valueToDefVecMap.find(srcI);
           if (I != valueToDefVecMap.end())
-            addEdgesForValue(node, (*I).second, minstr.getImplicitRef(i),
-                             minstr.implicitRefIsDefined(i),
-                             minstr.implicitRefIsDefinedAndUsed(i), target);
+            addEdgesForValue(node, I->second, srcI,
+                             MI.implicitRefIsDefined(i),
+                             MI.implicitRefIsDefinedAndUsed(i), target);
         }
 }
 
@@ -700,14 +699,14 @@
   
   // Collect the register references and value defs. for explicit operands
   // 
-  const MachineInstr& minstr = * node->getMachineInstr();
+  const MachineInstr& minstr = *node->getMachineInstr();
   for (int i=0, numOps = (int) minstr.getNumOperands(); i < numOps; i++)
     {
       const MachineOperand& mop = minstr.getOperand(i);
       
       // if this references a register other than the hardwired
       // "zero" register, record the reference.
-      if (mop.getOperandType() == MachineOperand::MO_MachineRegister)
+      if (mop.getType() == MachineOperand::MO_MachineRegister)
         {
           int regNum = mop.getMachineRegNum();
 	  if (regNum != target.getRegInfo().getZeroRegNum())
@@ -721,8 +720,8 @@
 	continue;
       
       // We must be defining a value.
-      assert((mop.getOperandType() == MachineOperand::MO_VirtualRegister ||
-              mop.getOperandType() == MachineOperand::MO_CCRegister)
+      assert((mop.getType() == MachineOperand::MO_VirtualRegister ||
+              mop.getType() == MachineOperand::MO_CCRegister)
              && "Do not expect any other kind of operand to be defined!");
       
       const Instruction* defInstr = cast<Instruction>(mop.getVRegValue());
diff --git a/lib/CodeGen/InstrSelection/InstrSelectionSupport.cpp b/lib/CodeGen/InstrSelection/InstrSelectionSupport.cpp
index 242d1dd..796d076 100644
--- a/lib/CodeGen/InstrSelection/InstrSelectionSupport.cpp
+++ b/lib/CodeGen/InstrSelection/InstrSelectionSupport.cpp
@@ -483,9 +483,9 @@
       // Skip the result position, preallocated machine registers, or operands
       // that cannot be constants (CC regs or PC-relative displacements)
       if (instrDesc.resultPos == (int) op ||
-          mop.getOperandType() == MachineOperand::MO_MachineRegister ||
-          mop.getOperandType() == MachineOperand::MO_CCRegister ||
-          mop.getOperandType() == MachineOperand::MO_PCRelativeDisp)
+          mop.getType() == MachineOperand::MO_MachineRegister ||
+          mop.getType() == MachineOperand::MO_CCRegister ||
+          mop.getType() == MachineOperand::MO_PCRelativeDisp)
         continue;
 
       bool constantThatMustBeLoaded = false;
@@ -496,7 +496,7 @@
         MachineOperand::MO_VirtualRegister;
 
       // Operand may be a virtual register or a compile-time constant
-      if (mop.getOperandType() == MachineOperand::MO_VirtualRegister)
+      if (mop.getType() == MachineOperand::MO_VirtualRegister)
         {
           assert(mop.getVRegValue() != NULL);
           opValue = mop.getVRegValue();
@@ -510,10 +510,10 @@
         }
       else
         {
-          assert(mop.getOperandType() == MachineOperand::MO_SignExtendedImmed ||
-                 mop.getOperandType() == MachineOperand::MO_UnextendedImmed);
+          assert(mop.getType() == MachineOperand::MO_SignExtendedImmed ||
+                 mop.getType() == MachineOperand::MO_UnextendedImmed);
 
-          bool isSigned = (mop.getOperandType() ==
+          bool isSigned = (mop.getType() ==
                            MachineOperand::MO_SignExtendedImmed);
 
           // Bit-selection flags indicate an instruction that is extracting
@@ -526,7 +526,7 @@
                                     opCode, target, (immedPos == (int)op), 
                                     machineRegNum, immedValue);
 
-          if (opType == mop.getOperandType()) 
+          if (opType == mop.getType()) 
             continue;           // no change: this is the most common case
 
           if (opType == MachineOperand::MO_VirtualRegister)
diff --git a/lib/CodeGen/RegAlloc/LiveRangeInfo.cpp b/lib/CodeGen/RegAlloc/LiveRangeInfo.cpp
index 31bd134..76f5594 100644
--- a/lib/CodeGen/RegAlloc/LiveRangeInfo.cpp
+++ b/lib/CodeGen/RegAlloc/LiveRangeInfo.cpp
@@ -110,7 +110,7 @@
 
   // check if the LR is already there (because of multiple defs)
   if (!DefRange) { 
-    DefRange = this->createNewLiveRange(Def, isCC);
+    DefRange = createNewLiveRange(Def, isCC);
   } else {                          // live range already exists
     DefRange->insert(Def);          // add the operand to the range
     LiveRangeMap[Def] = DefRange;   // make operand point to merged set
@@ -134,7 +134,7 @@
   // first find the live ranges for all incoming args of the function since
   // those LRs start from the start of the function
   for (Function::const_aiterator AI = Meth->abegin(); AI != Meth->aend(); ++AI)
-    this->createNewLiveRange(AI, /*isCC*/ false);
+    createNewLiveRange(AI, /*isCC*/ false);
 
   // Now suggest hardware registers for these function args 
   MRI.suggestRegs4MethodArgs(Meth, *this);
@@ -160,7 +160,7 @@
       // 
       if(TM.getInstrInfo().isReturn(MInst->getOpCode()) ||
 	 TM.getInstrInfo().isCall(MInst->getOpCode()))
-	CallRetInstrList.push_back( MInst ); 
+	CallRetInstrList.push_back(MInst); 
  
       // iterate over explicit MI operands and create a new LR
       // for each operand that is defined by the instruction
@@ -168,9 +168,9 @@
              OpE = MInst->end(); OpI != OpE; ++OpI)
 	if (OpI.isDef()) {     
 	  const Value *Def = *OpI;
-          bool isCC = (OpI.getMachineOperand().getOperandType()
+          bool isCC = (OpI.getMachineOperand().getType()
                        == MachineOperand::MO_CCRegister);
-          this->createOrAddToLiveRange(Def, isCC);
+          createOrAddToLiveRange(Def, isCC);
 	}
 
       // iterate over implicit MI operands and create a new LR
@@ -178,7 +178,7 @@
       for (unsigned i = 0; i < MInst->getNumImplicitRefs(); ++i) 
 	if (MInst->implicitRefIsDefined(i)) {     
 	  const Value *Def = MInst->getImplicitRef(i);
-          this->createOrAddToLiveRange(Def, /*isCC*/ false);
+          createOrAddToLiveRange(Def, /*isCC*/ false);
 	}
 
     } // for all machine instructions in the BB
diff --git a/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp b/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp
index 4dcd44f..9660e9f 100644
--- a/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp
+++ b/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp
@@ -539,8 +539,8 @@
       for (unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum)
         {
           MachineOperand& Op = MInst->getOperand(OpNum);
-          if (Op.getOperandType() ==  MachineOperand::MO_VirtualRegister || 
-              Op.getOperandType() ==  MachineOperand::MO_CCRegister)
+          if (Op.getType() ==  MachineOperand::MO_VirtualRegister || 
+              Op.getType() ==  MachineOperand::MO_CCRegister)
             {
               const Value *const Val =  Op.getVRegValue();
           
@@ -750,7 +750,7 @@
                                      std::vector<MachineInstr*>& MIBef,
                                      std::vector<MachineInstr*>& MIAft) {
   
-  RegClass* RC = this->getRegClassByID(MRI.getRegClassIDOfRegType(RegType));
+  RegClass* RC = getRegClassByID(MRI.getRegClassIDOfRegType(RegType));
   
   int RegU =  getUnusedUniRegAtMI(RC, MInst, LVSetBef);
   
@@ -766,8 +766,8 @@
     int scratchRegType = -1;
     if (MRI.regTypeNeedsScratchReg(RegType, scratchRegType))
       {
-        int scratchReg = this->getUsableUniRegAtMI(scratchRegType, LVSetBef,
-                                                   MInst, MIBef, MIAft);
+        int scratchReg = getUsableUniRegAtMI(scratchRegType, LVSetBef,
+                                             MInst, MIBef, MIAft);
         assert(scratchReg != MRI.getInvalidRegNum());
         
         // We may as well hold the value in the scratch register instead
@@ -893,8 +893,8 @@
     {
       const MachineOperand& Op = MInst->getOperand(OpNum);
       
-      if (Op.getOperandType() == MachineOperand::MO_VirtualRegister || 
-          Op.getOperandType() == MachineOperand::MO_CCRegister)
+      if (MInst->getOperandType(OpNum) == MachineOperand::MO_VirtualRegister || 
+          MInst->getOperandType(OpNum) == MachineOperand::MO_CCRegister)
         if (const Value* Val = Op.getVRegValue())
           if (MRI.getRegClassIDOfValue(Val) == RC->getID())
             if (Op.getAllocatedRegNum() == -1)
@@ -971,9 +971,9 @@
       for (unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum) {
 	MachineOperand& Op = MInst->getOperand(OpNum);
 
-	if (Op.getOperandType() ==  MachineOperand::MO_VirtualRegister || 
-	    Op.getOperandType() ==  MachineOperand::MO_CCRegister /*|| 
-	    Op.getOperandType() ==  MachineOperand::MO_PCRelativeDisp*/ ) {
+	if (Op.getType() ==  MachineOperand::MO_VirtualRegister || 
+	    Op.getType() ==  MachineOperand::MO_CCRegister /*|| 
+	    Op.getType() ==  MachineOperand::MO_PCRelativeDisp*/ ) {
 
 	  const Value *const Val = Op.getVRegValue () ;
 	  // ****this code is temporary till NULL Values are fixed
@@ -1005,7 +1005,7 @@
 	  }
 
 	} 
-	else if (Op.getOperandType() ==  MachineOperand::MO_MachineRegister) {
+	else if (Op.getType() ==  MachineOperand::MO_MachineRegister) {
 	  cerr << "\t" << "%" << MRI.getUnifiedRegName(Op.getMachineRegNum());
 	}