Added instregex support to TableGen subtarget emitter.
This allows the processor-specific machine model to override selected
base opcodes without any fanciness.
e.g. InstRW<[CoreXWriteVANDP], (instregex "VANDP")>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165180 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/utils/TableGen/SetTheory.cpp b/utils/TableGen/SetTheory.cpp
index 46e6db1..bdca9a6 100644
--- a/utils/TableGen/SetTheory.cpp
+++ b/utils/TableGen/SetTheory.cpp
@@ -294,7 +294,10 @@
// This is the first time we see Set. Find a suitable expander.
try {
const std::vector<Record*> &SC = Set->getSuperClasses();
- for (unsigned i = 0, e = SC.size(); i != e; ++i)
+ for (unsigned i = 0, e = SC.size(); i != e; ++i) {
+ // Skip unnamed superclasses.
+ if (!dynamic_cast<const StringInit *>(SC[i]->getNameInit()))
+ continue;
if (Expander *Exp = Expanders.lookup(SC[i]->getName())) {
// This breaks recursive definitions.
RecVec &EltVec = Expansions[Set];
@@ -303,6 +306,7 @@
EltVec.assign(Elts.begin(), Elts.end());
return &EltVec;
}
+ }
} catch (const std::string &Error) {
throw TGError(Set->getLoc(), Error);
}