Major update of the MicroBlaze backend. The new features are:
1. A delay slot filler that searches for valid instructions
to fill the delay slot with. Previously NOPs would always
be inserted into delay slots.
2. Support for MC based instruction printer added.
3. Support for MC based machine code generation and ELF
file generation. ELF file generation does not yet
completely work as much of the ELF support infrastructure
is still x86/x86-64 specific.
4. General clean up of the MBlaze backend code. Much of the
tablegen code has been cleanup and simplified.
Bug Fixes:
1. Removed duplicate periods from subtarget feature descriptions.
2. Many of the instructions had bad machine code information
in the tablegen files. Much of this has been fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116986 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/test/CodeGen/MBlaze/brind.ll b/test/CodeGen/MBlaze/brind.ll
index 7798e0f..4ec8605 100644
--- a/test/CodeGen/MBlaze/brind.ll
+++ b/test/CodeGen/MBlaze/brind.ll
@@ -28,32 +28,31 @@
label %L3,
label %L4,
label %L5 ]
- ; CHECK: br {{r[0-9]*}}
+ ; CHECK: brd {{r[0-9]*}}
L1:
%tmp.1 = add i32 %a, %b
br label %finish
- ; CHECK: br
+ ; CHECK: brid
L2:
%tmp.2 = sub i32 %a, %b
br label %finish
- ; CHECK: br
+ ; CHECK: brid
L3:
%tmp.3 = mul i32 %a, %b
br label %finish
- ; CHECK: br
+ ; CHECK: brid
L4:
%tmp.4 = sdiv i32 %a, %b
br label %finish
- ; CHECK: br
+ ; CHECK: brid
L5:
%tmp.5 = srem i32 %a, %b
br label %finish
- ; CHECK: br
finish:
%tmp.6 = phi i32 [ %tmp.1, %L1 ],
@@ -69,5 +68,5 @@
%tmp.8 = urem i32 %tmp.7, 5
br label %loop
- ; CHECK: br
+ ; CHECK: brid
}
diff --git a/test/CodeGen/MBlaze/cc.ll b/test/CodeGen/MBlaze/cc.ll
index aaa918f..b1eb22a 100644
--- a/test/CodeGen/MBlaze/cc.ll
+++ b/test/CodeGen/MBlaze/cc.ll
@@ -12,7 +12,7 @@
define void @params0_noret() {
; CHECK: params0_noret:
ret void
- ; CHECK-NOT: {{.* r3, r0, 1}}
+ ; CHECK-NOT: {{.* r3, .*, .*}}
; CHECK-NOT: {{.* r4, .*, .*}}
; CHECK: rtsd
}
@@ -20,81 +20,88 @@
define i8 @params0_8bitret() {
; CHECK: params0_8bitret:
ret i8 1
- ; CHECK: {{.* r3, r0, 1}}
+ ; CHECK-NOT: {{.* r3, .*, .*}}
; CHECK-NOT: {{.* r4, .*, .*}}
; CHECK: rtsd
+ ; CHECK: {{.* r3, r0, 1}}
}
define i16 @params0_16bitret() {
; CHECK: params0_16bitret:
ret i16 1
+ ; CHECK: rtsd
; CHECK: {{.* r3, r0, 1}}
; CHECK-NOT: {{.* r4, .*, .*}}
- ; CHECK: rtsd
}
define i32 @params0_32bitret() {
; CHECK: params0_32bitret:
ret i32 1
- ; CHECK: {{.* r3, r0, 1}}
; CHECK-NOT: {{.* r4, .*, .*}}
; CHECK: rtsd
+ ; CHECK: {{.* r3, r0, 1}}
}
define i64 @params0_64bitret() {
; CHECK: params0_64bitret:
ret i64 1
; CHECK: {{.* r3, r0, .*}}
- ; CHECK: {{.* r4, r0, 1}}
; CHECK: rtsd
+ ; CHECK: {{.* r4, r0, 1}}
}
define i32 @params1_32bitret(i32 %a) {
; CHECK: params1_32bitret:
ret i32 %a
- ; CHECK: {{.* r3, r5, r0}}
+ ; CHECK-NOT: {{.* r3, .*, .*}}
; CHECK-NOT: {{.* r4, .*, .*}}
; CHECK: rtsd
+ ; CHECK: {{.* r3, r5, r0}}
}
define i32 @params2_32bitret(i32 %a, i32 %b) {
; CHECK: params2_32bitret:
ret i32 %b
- ; CHECK: {{.* r3, r6, r0}}
+ ; CHECK-NOT: {{.* r3, .*, .*}}
; CHECK-NOT: {{.* r4, .*, .*}}
; CHECK: rtsd
+ ; CHECK: {{.* r3, r6, r0}}
}
define i32 @params3_32bitret(i32 %a, i32 %b, i32 %c) {
; CHECK: params3_32bitret:
ret i32 %c
- ; CHECK: {{.* r3, r7, r0}}
+ ; CHECK-NOT: {{.* r3, .*, .*}}
; CHECK-NOT: {{.* r4, .*, .*}}
; CHECK: rtsd
+ ; CHECK: {{.* r3, r7, r0}}
}
define i32 @params4_32bitret(i32 %a, i32 %b, i32 %c, i32 %d) {
; CHECK: params4_32bitret:
ret i32 %d
- ; CHECK: {{.* r3, r8, r0}}
+ ; CHECK-NOT: {{.* r3, .*, .*}}
; CHECK-NOT: {{.* r4, .*, .*}}
; CHECK: rtsd
+ ; CHECK: {{.* r3, r8, r0}}
}
define i32 @params5_32bitret(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
; CHECK: params5_32bitret:
ret i32 %e
- ; CHECK: {{.* r3, r9, r0}}
+ ; CHECK-NOT: {{.* r3, .*, .*}}
; CHECK-NOT: {{.* r4, .*, .*}}
; CHECK: rtsd
+ ; CHECK: {{.* r3, r9, r0}}
}
define i32 @params6_32bitret(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f) {
; CHECK: params6_32bitret:
ret i32 %f
- ; CHECK: {{.* r3, r10, r0}}
+ ; CHECK-NOT: {{.* r3, .*, .*}}
; CHECK-NOT: {{.* r4, .*, .*}}
; CHECK: rtsd
+ ; CHECK: {{.* r3, r10, r0}}
}
define i32 @params7_32bitret(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f,
@@ -142,53 +149,29 @@
%tmp.1 = call i8 @params0_8bitret()
; CHECK: brlid
call i32 (i8*,...)* @printf(i8* %MSG.1, i8 %tmp.1)
- ; CHECK: {{.* r5, .*, .*}}
- ; CHECK: {{.* r6, r3, r0}}
- ; CHECK-NOT: {{.* r7, .*, .*}}
- ; CHECK: brlid
%tmp.2 = call i16 @params0_16bitret()
; CHECK: brlid
call i32 (i8*,...)* @printf(i8* %MSG.1, i16 %tmp.2)
- ; CHECK: {{.* r5, .*, .*}}
- ; CHECK: {{.* r6, r3, r0}}
- ; CHECK-NOT: {{.* r7, .*, .*}}
- ; CHECK: brlid
%tmp.3 = call i32 @params0_32bitret()
; CHECK: brlid
call i32 (i8*,...)* @printf(i8* %MSG.1, i32 %tmp.3)
- ; CHECK: {{.* r5, .*, .*}}
- ; CHECK: {{.* r6, r3, r0}}
- ; CHECK-NOT: {{.* r7, .*, .*}}
- ; CHECK: brlid
%tmp.4 = call i64 @params0_64bitret()
; CHECK: brlid
call i32 (i8*,...)* @printf(i8* %MSG.1, i64 %tmp.4)
- ; CHECK: {{.* r5, .*, .*}}
- ; CHECK: {{.* r6, r3, r0}}
- ; CHECK: {{.* r7, r4, r0}}
- ; CHECK: brlid
%tmp.5 = call i32 @params1_32bitret(i32 1)
; CHECK: {{.* r5, .*, .*}}
; CHECK: brlid
call i32 (i8*,...)* @printf(i8* %MSG.1, i32 %tmp.5)
- ; CHECK: {{.* r5, .*, .*}}
- ; CHECK: {{.* r6, r3, r0}}
- ; CHECK-NOT: {{.* r7, .*, .*}}
- ; CHECK: brlid
%tmp.6 = call i32 @params2_32bitret(i32 1, i32 2)
; CHECK: {{.* r5, .*, .*}}
; CHECK: {{.* r6, .*, .*}}
; CHECK: brlid
call i32 (i8*,...)* @printf(i8* %MSG.1, i32 %tmp.6)
- ; CHECK: {{.* r5, .*, .*}}
- ; CHECK: {{.* r6, r3, r0}}
- ; CHECK-NOT: {{.* r7, .*, .*}}
- ; CHECK: brlid
%tmp.7 = call i32 @params3_32bitret(i32 1, i32 2, i32 3)
; CHECK: {{.* r5, .*, .*}}
@@ -196,10 +179,6 @@
; CHECK: {{.* r7, .*, .*}}
; CHECK: brlid
call i32 (i8*,...)* @printf(i8* %MSG.1, i32 %tmp.7)
- ; CHECK: {{.* r5, .*, .*}}
- ; CHECK: {{.* r6, r3, r0}}
- ; CHECK-NOT: {{.* r7, .*, .*}}
- ; CHECK: brlid
%tmp.8 = call i32 @params4_32bitret(i32 1, i32 2, i32 3, i32 4)
; CHECK: {{.* r5, .*, .*}}
@@ -208,10 +187,6 @@
; CHECK: {{.* r8, .*, .*}}
; CHECK: brlid
call i32 (i8*,...)* @printf(i8* %MSG.1, i32 %tmp.8)
- ; CHECK: {{.* r5, .*, .*}}
- ; CHECK: {{.* r6, r3, r0}}
- ; CHECK-NOT: {{.* r7, .*, .*}}
- ; CHECK: brlid
%tmp.9 = call i32 @params5_32bitret(i32 1, i32 2, i32 3, i32 4, i32 5)
; CHECK: {{.* r5, .*, .*}}
@@ -221,10 +196,6 @@
; CHECK: {{.* r9, .*, .*}}
; CHECK: brlid
call i32 (i8*,...)* @printf(i8* %MSG.1, i32 %tmp.9)
- ; CHECK: {{.* r5, .*, .*}}
- ; CHECK: {{.* r6, r3, r0}}
- ; CHECK-NOT: {{.* r7, .*, .*}}
- ; CHECK: brlid
%tmp.10 = call i32 @params6_32bitret(i32 1, i32 2, i32 3, i32 4, i32 5,
i32 6)
@@ -236,10 +207,6 @@
; CHECK: {{.* r10, .*, .*}}
; CHECK: brlid
call i32 (i8*,...)* @printf(i8* %MSG.1, i32 %tmp.10)
- ; CHECK: {{.* r5, .*, .*}}
- ; CHECK: {{.* r6, r3, r0}}
- ; CHECK-NOT: {{.* r7, .*, .*}}
- ; CHECK: brlid
%tmp.11 = call i32 @params7_32bitret(i32 1, i32 2, i32 3, i32 4, i32 5,
i32 6, i32 7)
@@ -252,10 +219,6 @@
; CHECK: {{.* r10, .*, .*}}
; CHECK: brlid
call i32 (i8*,...)* @printf(i8* %MSG.1, i32 %tmp.11)
- ; CHECK: {{.* r5, .*, .*}}
- ; CHECK: {{.* r6, r3, r0}}
- ; CHECK-NOT: {{.* r7, .*, .*}}
- ; CHECK: brlid
%tmp.12 = call i32 @params8_32bitret(i32 1, i32 2, i32 3, i32 4, i32 5,
i32 6, i32 7, i32 8)
@@ -269,10 +232,6 @@
; CHECK: {{.* r10, .*, .*}}
; CHECK: brlid
call i32 (i8*,...)* @printf(i8* %MSG.1, i32 %tmp.12)
- ; CHECK: {{.* r5, .*, .*}}
- ; CHECK: {{.* r6, r3, r0}}
- ; CHECK-NOT: {{.* r7, .*, .*}}
- ; CHECK: brlid
%tmp.13 = call i32 @params9_32bitret(i32 1, i32 2, i32 3, i32 4, i32 5,
i32 6, i32 7, i32 8, i32 9)
@@ -287,10 +246,6 @@
; CHECK: {{.* r10, .*, .*}}
; CHECK: brlid
call i32 (i8*,...)* @printf(i8* %MSG.1, i32 %tmp.13)
- ; CHECK: {{.* r5, .*, .*}}
- ; CHECK: {{.* r6, r3, r0}}
- ; CHECK-NOT: {{.* r7, .*, .*}}
- ; CHECK: brlid
%tmp.14 = call i32 @params10_32bitret(i32 1, i32 2, i32 3, i32 4, i32 5,
i32 6, i32 7, i32 8, i32 9, i32 10)
@@ -306,10 +261,6 @@
; CHECK: {{.* r10, .*, .*}}
; CHECK: brlid
call i32 (i8*,...)* @printf(i8* %MSG.1, i32 %tmp.14)
- ; CHECK: {{.* r5, .*, .*}}
- ; CHECK: {{.* r6, r3, r0}}
- ; CHECK-NOT: {{.* r7, .*, .*}}
- ; CHECK: brlid
ret void
}
diff --git a/test/CodeGen/MBlaze/fpu.ll b/test/CodeGen/MBlaze/fpu.ll
index 83f4d83..2aef4fd 100644
--- a/test/CodeGen/MBlaze/fpu.ll
+++ b/test/CodeGen/MBlaze/fpu.ll
@@ -10,14 +10,14 @@
; FPU: test_add:
%tmp.1 = fadd float %a, %b
- ; FUN-NOT: fadd
; FUN: brlid
; FPU-NOT: brlid
- ; FPU: fadd
ret float %tmp.1
; FUN: rtsd
; FPU: rtsd
+ ; FUN-NOT: fadd
+ ; FPU-NEXT: fadd
}
define float @test_sub(float %a, float %b) {
@@ -25,14 +25,14 @@
; FPU: test_sub:
%tmp.1 = fsub float %a, %b
- ; FUN-NOT: frsub
; FUN: brlid
; FPU-NOT: brlid
- ; FPU: frsub
ret float %tmp.1
; FUN: rtsd
; FPU: rtsd
+ ; FUN-NOT: frsub
+ ; FPU-NEXT: frsub
}
define float @test_mul(float %a, float %b) {
@@ -40,14 +40,14 @@
; FPU: test_mul:
%tmp.1 = fmul float %a, %b
- ; FUN-NOT: fmul
; FUN: brlid
; FPU-NOT: brlid
- ; FPU: fmul
ret float %tmp.1
; FUN: rtsd
; FPU: rtsd
+ ; FUN-NOT: fmul
+ ; FPU-NEXT: fmul
}
define float @test_div(float %a, float %b) {
@@ -55,12 +55,12 @@
; FPU: test_div:
%tmp.1 = fdiv float %a, %b
- ; FUN-NOT: fdiv
; FUN: brlid
; FPU-NOT: brlid
- ; FPU: fdiv
ret float %tmp.1
; FUN: rtsd
; FPU: rtsd
+ ; FUN-NOT: fdiv
+ ; FPU-NEXT: fdiv
}
diff --git a/test/CodeGen/MBlaze/imm.ll b/test/CodeGen/MBlaze/imm.ll
index 85fad17..7574687 100644
--- a/test/CodeGen/MBlaze/imm.ll
+++ b/test/CodeGen/MBlaze/imm.ll
@@ -7,21 +7,21 @@
define i8 @retimm_i8() {
; CHECK: retimm_i8:
- ; CHECK: add
- ; CHECK-NEXT: rtsd
+ ; CHECK: rtsd
+ ; CHECK-NEXT: add
; FPU: retimm_i8:
- ; FPU: add
- ; FPU-NEXT: rtsd
+ ; FPU: rtsd
+ ; FPU-NEXT: add
ret i8 123
}
define i16 @retimm_i16() {
; CHECK: retimm_i16:
- ; CHECK: add
- ; CHECK-NEXT: rtsd
+ ; CHECK: rtsd
+ ; CHECK-NEXT: add
; FPU: retimm_i16:
- ; FPU: add
- ; FPU-NEXT: rtsd
+ ; FPU: rtsd
+ ; FPU-NEXT: add
ret i16 38212
}
@@ -38,12 +38,12 @@
define i64 @retimm_i64() {
; CHECK: retimm_i64:
; CHECK: add
- ; CHECK-NEXT: add
; CHECK-NEXT: rtsd
+ ; CHECK-NEXT: add
; FPU: retimm_i64:
; FPU: add
- ; FPU-NEXT: add
; FPU-NEXT: rtsd
+ ; FPU-NEXT: add
ret i64 94581823
}
@@ -53,7 +53,7 @@
; CHECK-NEXT: rtsd
; FPU: retimm_float:
; FPU: or
- ; FPU: rtsd
+ ; FPU-NEXT: rtsd
ret float 12.0
}
diff --git a/test/CodeGen/MBlaze/jumptable.ll b/test/CodeGen/MBlaze/jumptable.ll
index 3f27c12..0861810 100644
--- a/test/CodeGen/MBlaze/jumptable.ll
+++ b/test/CodeGen/MBlaze/jumptable.ll
@@ -18,8 +18,8 @@
i32 8, label %L8
i32 9, label %L9 ]
- ; CHECK: lw [[REG:r[0-9]*]]
- ; CHECK: br [[REG]]
+ ; CHECK: lw [[REG:r[0-9]*]]
+ ; CHECK: brd [[REG]]
L0:
%var0 = add i32 %arg, 0
br label %DONE
diff --git a/test/CodeGen/MBlaze/mul.ll b/test/CodeGen/MBlaze/mul.ll
index 65d3e22..cefdb8d 100644
--- a/test/CodeGen/MBlaze/mul.ll
+++ b/test/CodeGen/MBlaze/mul.ll
@@ -13,11 +13,11 @@
; FUN-NOT: mul
; FUN: brlid
; MUL-NOT: brlid
- ; MUL: mul
ret i8 %tmp.1
; FUN: rtsd
; MUL: rtsd
+ ; MUL: mul
}
define i16 @test_i16(i16 %a, i16 %b) {
@@ -28,11 +28,11 @@
; FUN-NOT: mul
; FUN: brlid
; MUL-NOT: brlid
- ; MUL: mul
ret i16 %tmp.1
; FUN: rtsd
; MUL: rtsd
+ ; MUL: mul
}
define i32 @test_i32(i32 %a, i32 %b) {
@@ -43,9 +43,9 @@
; FUN-NOT: mul
; FUN: brlid
; MUL-NOT: brlid
- ; MUL: mul
ret i32 %tmp.1
; FUN: rtsd
; MUL: rtsd
+ ; MUL: mul
}
diff --git a/test/CodeGen/MBlaze/shift.ll b/test/CodeGen/MBlaze/shift.ll
index 186115e..7eac641 100644
--- a/test/CodeGen/MBlaze/shift.ll
+++ b/test/CodeGen/MBlaze/shift.ll
@@ -10,17 +10,17 @@
; SHT: test_i8:
%tmp.1 = shl i8 %a, %b
- ; FUN-NOT: bsll
; FUN: andi
; FUN: add
; FUN: bnei
; SHT-NOT: andi
; SHT-NOT: bnei
- ; SHT: bsll
ret i8 %tmp.1
; FUN: rtsd
; SHT: rtsd
+ ; FUN-NOT: bsll
+ ; SHT-NEXT: bsll
}
define i8 @testc_i8(i8 %a, i8 %b) {
@@ -28,18 +28,18 @@
; SHT: testc_i8:
%tmp.1 = shl i8 %a, 5
- ; FUN-NOT: bsll
; FUN: andi
; FUN: add
; FUN: bnei
; SHT-NOT: andi
; SHT-NOT: add
; SHT-NOT: bnei
- ; SHT: bslli
ret i8 %tmp.1
; FUN: rtsd
; SHT: rtsd
+ ; FUN-NOT: bsll
+ ; SHT-NEXT: bslli
}
define i16 @test_i16(i16 %a, i16 %b) {
@@ -47,17 +47,17 @@
; SHT: test_i16:
%tmp.1 = shl i16 %a, %b
- ; FUN-NOT: bsll
; FUN: andi
; FUN: add
; FUN: bnei
; SHT-NOT: andi
; SHT-NOT: bnei
- ; SHT: bsll
ret i16 %tmp.1
; FUN: rtsd
; SHT: rtsd
+ ; FUN-NOT: bsll
+ ; SHT-NEXT: bsll
}
define i16 @testc_i16(i16 %a, i16 %b) {
@@ -65,18 +65,18 @@
; SHT: testc_i16:
%tmp.1 = shl i16 %a, 5
- ; FUN-NOT: bsll
; FUN: andi
; FUN: add
; FUN: bnei
; SHT-NOT: andi
; SHT-NOT: add
; SHT-NOT: bnei
- ; SHT: bslli
ret i16 %tmp.1
; FUN: rtsd
; SHT: rtsd
+ ; FUN-NOT: bsll
+ ; SHT-NEXT: bslli
}
define i32 @test_i32(i32 %a, i32 %b) {
@@ -84,17 +84,17 @@
; SHT: test_i32:
%tmp.1 = shl i32 %a, %b
- ; FUN-NOT: bsll
; FUN: andi
; FUN: add
; FUN: bnei
; SHT-NOT: andi
; SHT-NOT: bnei
- ; SHT: bsll
ret i32 %tmp.1
; FUN: rtsd
; SHT: rtsd
+ ; FUN-NOT: bsll
+ ; SHT-NEXT: bsll
}
define i32 @testc_i32(i32 %a, i32 %b) {
@@ -102,16 +102,16 @@
; SHT: testc_i32:
%tmp.1 = shl i32 %a, 5
- ; FUN-NOT: bsll
; FUN: andi
; FUN: add
; FUN: bnei
; SHT-NOT: andi
; SHT-NOT: add
; SHT-NOT: bnei
- ; SHT: bslli
ret i32 %tmp.1
; FUN: rtsd
; SHT: rtsd
+ ; FUN-NOT: bsll
+ ; SHT-NEXT: bslli
}