ARM parsing for VLD1 two register all lanes, no writeback.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145504 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/utils/TableGen/EDEmitter.cpp b/utils/TableGen/EDEmitter.cpp
index 04ee738..22de377 100644
--- a/utils/TableGen/EDEmitter.cpp
+++ b/utils/TableGen/EDEmitter.cpp
@@ -577,6 +577,7 @@
   REG("VecListFourD");
   REG("VecListTwoQ");
   REG("VecListOneDAllLanes");
+  REG("VecListTwoDAllLanes");
 
   IMM("i32imm");
   IMM("i32imm_hilo16");