Move the point at which FastISel taps into the SelectionDAGISel
process up to a higher level. This allows FastISel to leverage
more of SelectionDAGISel's infastructure, such as updating Machine
PHI nodes.
Also, implement transitioning from SDISel back to FastISel in
the middle of a block, so it's now possible to go back and
forth. This allows FastISel to hand individual CallInsts and other
complicated things off to SDISel to handle, while handling the rest
of the block itself.
To help support this, reorganize the SelectionDAG class so that it
is allocated once and reused throughout a function, instead of
being completely reallocated for each block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55219 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp
index ad1f63d..d26a5fb 100644
--- a/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -54,7 +54,7 @@
}
SDNode *Select(SDValue Op);
- virtual void InstructionSelect(SelectionDAG &DAG);
+ virtual void InstructionSelect();
bool SelectAddrMode2(SDValue Op, SDValue N, SDValue &Base,
SDValue &Offset, SDValue &Opc);
bool SelectAddrMode2Offset(SDValue Op, SDValue N,
@@ -91,11 +91,11 @@
};
}
-void ARMDAGToDAGISel::InstructionSelect(SelectionDAG &DAG) {
+void ARMDAGToDAGISel::InstructionSelect() {
DEBUG(BB->dump());
SelectRoot();
- DAG.RemoveDeadNodes();
+ CurDAG->RemoveDeadNodes();
}
bool ARMDAGToDAGISel::SelectAddrMode2(SDValue Op, SDValue N,
diff --git a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
index 0ff735d..ce6afc3 100644
--- a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
+++ b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
@@ -163,7 +163,7 @@
/// InstructionSelect - This callback is invoked by
/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
- virtual void InstructionSelect(SelectionDAG &DAG);
+ virtual void InstructionSelect();
virtual const char *getPassName() const {
return "Alpha DAG->DAG Pattern Instruction Selection";
@@ -173,8 +173,7 @@
/// inline asm expressions.
virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
char ConstraintCode,
- std::vector<SDValue> &OutOps,
- SelectionDAG &DAG) {
+ std::vector<SDValue> &OutOps) {
SDValue Op0;
switch (ConstraintCode) {
default: return true;
@@ -232,12 +231,12 @@
/// InstructionSelect - This callback is invoked by
/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
-void AlphaDAGToDAGISel::InstructionSelect(SelectionDAG &DAG) {
+void AlphaDAGToDAGISel::InstructionSelect() {
DEBUG(BB->dump());
// Select target instructions for the DAG.
SelectRoot();
- DAG.RemoveDeadNodes();
+ CurDAG->RemoveDeadNodes();
}
// Select - Convert the specified operand from a target-independent to a
diff --git a/lib/Target/CellSPU/SPUISelDAGToDAG.cpp b/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
index c8d04b4..c2a3e3a 100644
--- a/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
+++ b/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
@@ -285,8 +285,7 @@
/// inline asm expressions.
virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
char ConstraintCode,
- std::vector<SDValue> &OutOps,
- SelectionDAG &DAG) {
+ std::vector<SDValue> &OutOps) {
SDValue Op0, Op1;
switch (ConstraintCode) {
default: return true;
@@ -319,7 +318,7 @@
/// InstructionSelect - This callback is invoked by
/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
- virtual void InstructionSelect(SelectionDAG &DAG);
+ virtual void InstructionSelect();
virtual const char *getPassName() const {
return "Cell SPU DAG->DAG Pattern Instruction Selection";
@@ -342,13 +341,13 @@
/// InstructionSelect - This callback is invoked by
/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
void
-SPUDAGToDAGISel::InstructionSelect(SelectionDAG &DAG)
+SPUDAGToDAGISel::InstructionSelect()
{
DEBUG(BB->dump());
// Select target instructions for the DAG.
SelectRoot();
- DAG.RemoveDeadNodes();
+ CurDAG->RemoveDeadNodes();
}
/*!
diff --git a/lib/Target/IA64/IA64ISelDAGToDAG.cpp b/lib/Target/IA64/IA64ISelDAGToDAG.cpp
index 8173e96..aa1f6bb 100644
--- a/lib/Target/IA64/IA64ISelDAGToDAG.cpp
+++ b/lib/Target/IA64/IA64ISelDAGToDAG.cpp
@@ -80,7 +80,7 @@
/// InstructionSelect - This callback is invoked by
/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
- virtual void InstructionSelect(SelectionDAG &DAG);
+ virtual void InstructionSelect();
virtual const char *getPassName() const {
return "IA64 (Itanium) DAG->DAG Instruction Selector";
@@ -96,12 +96,12 @@
/// InstructionSelect - This callback is invoked by
/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
-void IA64DAGToDAGISel::InstructionSelect(SelectionDAG &DAG) {
+void IA64DAGToDAGISel::InstructionSelect() {
DEBUG(BB->dump());
// Select target instructions for the DAG.
SelectRoot();
- DAG.RemoveDeadNodes();
+ CurDAG->RemoveDeadNodes();
}
SDNode *IA64DAGToDAGISel::SelectDIV(SDValue Op) {
diff --git a/lib/Target/Mips/MipsISelDAGToDAG.cpp b/lib/Target/Mips/MipsISelDAGToDAG.cpp
index 94fdb35..1e07a8f 100644
--- a/lib/Target/Mips/MipsISelDAGToDAG.cpp
+++ b/lib/Target/Mips/MipsISelDAGToDAG.cpp
@@ -66,7 +66,7 @@
TM(tm), MipsLowering(*TM.getTargetLowering()),
Subtarget(tm.getSubtarget<MipsSubtarget>()) {}
- virtual void InstructionSelect(SelectionDAG &SD);
+ virtual void InstructionSelect();
// Pass Name
virtual const char *getPassName() const {
@@ -103,7 +103,7 @@
/// InstructionSelect - This callback is invoked by
/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
void MipsDAGToDAGISel::
-InstructionSelect(SelectionDAG &SD)
+InstructionSelect()
{
DEBUG(BB->dump());
// Codegen the basic block.
@@ -119,7 +119,7 @@
DOUT << "===== Instruction selection ends:\n";
#endif
- SD.RemoveDeadNodes();
+ CurDAG->RemoveDeadNodes();
}
/// getGlobalBaseReg - Output the instructions required to put the
diff --git a/lib/Target/PIC16/PIC16ISelDAGToDAG.cpp b/lib/Target/PIC16/PIC16ISelDAGToDAG.cpp
index f1eaa39..a9c1d09 100644
--- a/lib/Target/PIC16/PIC16ISelDAGToDAG.cpp
+++ b/lib/Target/PIC16/PIC16ISelDAGToDAG.cpp
@@ -60,7 +60,7 @@
SelectionDAGISel(PIC16Lowering),
TM(tm), PIC16Lowering(*TM.getTargetLowering()) {}
- virtual void InstructionSelect(SelectionDAG &SD);
+ virtual void InstructionSelect();
// Pass Name
virtual const char *getPassName() const {
@@ -98,7 +98,7 @@
/// InstructionSelect - This callback is invoked by
/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
-void PIC16DAGToDAGISel::InstructionSelect(SelectionDAG &SD)
+void PIC16DAGToDAGISel::InstructionSelect()
{
DEBUG(BB->dump());
// Codegen the basic block.
@@ -113,7 +113,7 @@
DOUT << "===== Instruction selection ends:\n";
- SD.RemoveDeadNodes();
+ CurDAG->RemoveDeadNodes();
}
diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index c647955..e655e06 100644
--- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -144,8 +144,7 @@
/// inline asm expressions.
virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
char ConstraintCode,
- std::vector<SDValue> &OutOps,
- SelectionDAG &DAG) {
+ std::vector<SDValue> &OutOps) {
SDValue Op0, Op1;
switch (ConstraintCode) {
default: return true;
@@ -175,7 +174,7 @@
/// InstructionSelect - This callback is invoked by
/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
- virtual void InstructionSelect(SelectionDAG &DAG);
+ virtual void InstructionSelect();
void InsertVRSaveCode(Function &Fn);
@@ -203,12 +202,12 @@
/// InstructionSelect - This callback is invoked by
/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
-void PPCDAGToDAGISel::InstructionSelect(SelectionDAG &DAG) {
+void PPCDAGToDAGISel::InstructionSelect() {
DEBUG(BB->dump());
// Select target instructions for the DAG.
SelectRoot();
- DAG.RemoveDeadNodes();
+ CurDAG->RemoveDeadNodes();
}
/// InsertVRSaveCode - Once the entire function has been instruction selected,
diff --git a/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/lib/Target/Sparc/SparcISelDAGToDAG.cpp
index f623873..64e9bce 100644
--- a/lib/Target/Sparc/SparcISelDAGToDAG.cpp
+++ b/lib/Target/Sparc/SparcISelDAGToDAG.cpp
@@ -49,7 +49,7 @@
/// InstructionSelect - This callback is invoked by
/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
- virtual void InstructionSelect(SelectionDAG &DAG);
+ virtual void InstructionSelect();
virtual const char *getPassName() const {
return "SPARC DAG->DAG Pattern Instruction Selection";
@@ -62,12 +62,12 @@
/// InstructionSelect - This callback is invoked by
/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
-void SparcDAGToDAGISel::InstructionSelect(SelectionDAG &DAG) {
+void SparcDAGToDAGISel::InstructionSelect() {
DEBUG(BB->dump());
// Select target instructions for the DAG.
SelectRoot();
- DAG.RemoveDeadNodes();
+ CurDAG->RemoveDeadNodes();
}
bool SparcDAGToDAGISel::SelectADDRri(SDValue Op, SDValue Addr,
diff --git a/lib/Target/X86/X86ISelDAGToDAG.cpp b/lib/Target/X86/X86ISelDAGToDAG.cpp
index 21837d5..29986e5 100644
--- a/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -147,7 +147,7 @@
/// InstructionSelect - This callback is invoked by
/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
- virtual void InstructionSelect(SelectionDAG &DAG);
+ virtual void InstructionSelect();
/// InstructionSelectPostProcessing - Post processing of selected and
/// scheduled basic blocks.
@@ -178,15 +178,14 @@
bool TryFoldLoad(SDValue P, SDValue N,
SDValue &Base, SDValue &Scale,
SDValue &Index, SDValue &Disp);
- void PreprocessForRMW(SelectionDAG &DAG);
- void PreprocessForFPConvert(SelectionDAG &DAG);
+ void PreprocessForRMW();
+ void PreprocessForFPConvert();
/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
/// inline asm expressions.
virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
char ConstraintCode,
- std::vector<SDValue> &OutOps,
- SelectionDAG &DAG);
+ std::vector<SDValue> &OutOps);
void EmitSpecialCodeForMain(MachineBasicBlock *BB, MachineFrameInfo *MFI);
@@ -372,7 +371,7 @@
/// MoveBelowTokenFactor - Replace TokenFactor operand with load's chain operand
/// and move load below the TokenFactor. Replace store's chain operand with
/// load's chain result.
-static void MoveBelowTokenFactor(SelectionDAG &DAG, SDValue Load,
+static void MoveBelowTokenFactor(SelectionDAG *CurDAG, SDValue Load,
SDValue Store, SDValue TF) {
std::vector<SDValue> Ops;
for (unsigned i = 0, e = TF.Val->getNumOperands(); i != e; ++i)
@@ -380,10 +379,10 @@
Ops.push_back(Load.Val->getOperand(0));
else
Ops.push_back(TF.Val->getOperand(i));
- DAG.UpdateNodeOperands(TF, &Ops[0], Ops.size());
- DAG.UpdateNodeOperands(Load, TF, Load.getOperand(1), Load.getOperand(2));
- DAG.UpdateNodeOperands(Store, Load.getValue(1), Store.getOperand(1),
- Store.getOperand(2), Store.getOperand(3));
+ CurDAG->UpdateNodeOperands(TF, &Ops[0], Ops.size());
+ CurDAG->UpdateNodeOperands(Load, TF, Load.getOperand(1), Load.getOperand(2));
+ CurDAG->UpdateNodeOperands(Store, Load.getValue(1), Store.getOperand(1),
+ Store.getOperand(2), Store.getOperand(3));
}
/// isRMWLoad - Return true if N is a load that's part of RMW sub-DAG.
@@ -452,9 +451,9 @@
/// \ /
/// \ /
/// [Store]
-void X86DAGToDAGISel::PreprocessForRMW(SelectionDAG &DAG) {
- for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
- E = DAG.allnodes_end(); I != E; ++I) {
+void X86DAGToDAGISel::PreprocessForRMW() {
+ for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
+ E = CurDAG->allnodes_end(); I != E; ++I) {
if (!ISD::isNON_TRUNCStore(I))
continue;
SDValue Chain = I->getOperand(0);
@@ -504,7 +503,7 @@
}
if (RModW) {
- MoveBelowTokenFactor(DAG, Load, SDValue(I, 0), Chain);
+ MoveBelowTokenFactor(CurDAG, Load, SDValue(I, 0), Chain);
++NumLoadMoved;
}
}
@@ -519,9 +518,9 @@
/// hack on these between the call expansion and the node legalization. As such
/// this pass basically does "really late" legalization of these inline with the
/// X86 isel pass.
-void X86DAGToDAGISel::PreprocessForFPConvert(SelectionDAG &DAG) {
- for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
- E = DAG.allnodes_end(); I != E; ) {
+void X86DAGToDAGISel::PreprocessForFPConvert() {
+ for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
+ E = CurDAG->allnodes_end(); I != E; ) {
SDNode *N = I++; // Preincrement iterator to avoid invalidation issues.
if (N->getOpcode() != ISD::FP_ROUND && N->getOpcode() != ISD::FP_EXTEND)
continue;
@@ -553,39 +552,40 @@
else
MemVT = SrcIsSSE ? SrcVT : DstVT;
- SDValue MemTmp = DAG.CreateStackTemporary(MemVT);
+ SDValue MemTmp = CurDAG->CreateStackTemporary(MemVT);
// FIXME: optimize the case where the src/dest is a load or store?
- SDValue Store = DAG.getTruncStore(DAG.getEntryNode(), N->getOperand(0),
- MemTmp, NULL, 0, MemVT);
- SDValue Result = DAG.getExtLoad(ISD::EXTLOAD, DstVT, Store, MemTmp,
- NULL, 0, MemVT);
+ SDValue Store = CurDAG->getTruncStore(CurDAG->getEntryNode(),
+ N->getOperand(0),
+ MemTmp, NULL, 0, MemVT);
+ SDValue Result = CurDAG->getExtLoad(ISD::EXTLOAD, DstVT, Store, MemTmp,
+ NULL, 0, MemVT);
// We're about to replace all uses of the FP_ROUND/FP_EXTEND with the
// extload we created. This will cause general havok on the dag because
// anything below the conversion could be folded into other existing nodes.
// To avoid invalidating 'I', back it up to the convert node.
--I;
- DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result);
+ CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), Result);
// Now that we did that, the node is dead. Increment the iterator to the
// next node to process, then delete N.
++I;
- DAG.DeleteNode(N);
+ CurDAG->DeleteNode(N);
}
}
/// InstructionSelectBasicBlock - This callback is invoked by SelectionDAGISel
/// when it has created a SelectionDAG for us to codegen.
-void X86DAGToDAGISel::InstructionSelect(SelectionDAG &DAG) {
+void X86DAGToDAGISel::InstructionSelect() {
CurBB = BB; // BB can change as result of isel.
DEBUG(BB->dump());
if (!Fast)
- PreprocessForRMW(DAG);
+ PreprocessForRMW();
// FIXME: This should only happen when not -fast.
- PreprocessForFPConvert(DAG);
+ PreprocessForFPConvert();
// Codegen the basic block.
#ifndef NDEBUG
@@ -597,7 +597,7 @@
DOUT << "===== Instruction selection ends:\n";
#endif
- DAG.RemoveDeadNodes();
+ CurDAG->RemoveDeadNodes();
}
void X86DAGToDAGISel::InstructionSelectPostProcessing() {
@@ -1599,7 +1599,7 @@
bool X86DAGToDAGISel::
SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
- std::vector<SDValue> &OutOps, SelectionDAG &DAG){
+ std::vector<SDValue> &OutOps) {
SDValue Op0, Op1, Op2, Op3;
switch (ConstraintCode) {
case 'o': // offsetable ??