Instead of adding dependence edges between terminator instructions
and every other instruction in their blocks to keep the terminator
instructions at the end, teach the post-RA scheduler how to operate
on ranges of instructions, and exclude terminators from the range
of instructions that get scheduled.
Also, exclude mid-block labels, such as EH_LABEL instructions, and
schedule code before them separately from code after them. This
fixes problems with the post-RA scheduler moving code past
EH_LABELs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62366 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/ScheduleDAGEmit.cpp b/lib/CodeGen/ScheduleDAGEmit.cpp
index d5bc67a..0c8435d 100644
--- a/lib/CodeGen/ScheduleDAGEmit.cpp
+++ b/lib/CodeGen/ScheduleDAGEmit.cpp
@@ -33,7 +33,7 @@
}
void ScheduleDAG::EmitNoop() {
- TII->insertNoop(*BB, BB->end());
+ TII->insertNoop(*BB, End);
}
void ScheduleDAG::EmitPhysRegCopy(SUnit *SU,
@@ -54,7 +54,7 @@
break;
}
}
- TII->copyRegToReg(*BB, BB->end(), Reg, VRI->second,
+ TII->copyRegToReg(*BB, End, Reg, VRI->second,
SU->CopyDstRC, SU->CopySrcRC);
} else {
// Copy from physical register.
@@ -63,7 +63,7 @@
bool isNew = VRBaseMap.insert(std::make_pair(SU, VRBase)).second;
isNew = isNew; // Silence compiler warning.
assert(isNew && "Node emitted out of order - early");
- TII->copyRegToReg(*BB, BB->end(), VRBase, I->getReg(),
+ TII->copyRegToReg(*BB, End, VRBase, I->getReg(),
SU->CopyDstRC, SU->CopySrcRC);
}
break;