commit 14f30c927dd6ad12974df653c681d21524c532f1
author Andrew Lenharth <andrewl@lenharth.org> Tue May 31 18:37:16 2005 +0000
committer Andrew Lenharth <andrewl@lenharth.org> Tue May 31 18:37:16 2005 +0000
tree c80d97138ef129ac8aad2ec107bf86caa96717b8
parent fd5e4b778f6c1b3660f341b87374042780b4aca0

switch to the new live in thing


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22186 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/Alpha/AlphaISelPattern.cpp

diff --git a/lib/Target/Alpha/AlphaISelPattern.cpp b/lib/Target/Alpha/AlphaISelPattern.cpp
index 59c5998..deed190 100644
--- a/lib/Target/Alpha/AlphaISelPattern.cpp
+++ b/lib/Target/Alpha/AlphaISelPattern.cpp
@@ -212,8 +212,8 @@
       case MVT::i64:
         args_int[count] = AddLiveIn(MF, args_int[count], getRegClassFor(VT));
         argt = DAG.getCopyFromReg(args_int[count], VT, DAG.getRoot());
-        //        if (VT != MVT::i64)
-        //          argt = DAG.getNode(ISD::TRUNCATE, VT, argt);
+        if (VT != MVT::i64)
+          argt = DAG.getNode(ISD::TRUNCATE, VT, argt);
         break;
       }
       DAG.setRoot(argt.getValue(1));