fix the !eq operator in tblgen to return a bit instead of an int.
Use this to make the X86 and ARM targets set isCodeGenOnly=1
automatically for their instructions that have Format=Pseudo,
resolving a hack in tblgen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117862 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/utils/TableGen/AsmMatcherEmitter.cpp b/utils/TableGen/AsmMatcherEmitter.cpp
index 0fad96e..6ddccc2 100644
--- a/utils/TableGen/AsmMatcherEmitter.cpp
+++ b/utils/TableGen/AsmMatcherEmitter.cpp
@@ -223,21 +223,6 @@
if (CGI.TheDef->getValueAsBit("isCodeGenOnly"))
return false;
- // Ignore pseudo ops.
- //
- // FIXME: This is a hack [for X86]; can we convert these instructions to set
- // the "codegen only" bit instead?
- if (const RecordVal *Form = CGI.TheDef->getValue("Form"))
- if (Form->getValue()->getAsString() == "Pseudo")
- return false;
-
- // FIXME: This is a hack [for ARM]; can we convert these instructions to set
- // the "codegen only" bit instead?
- if (const RecordVal *Form = CGI.TheDef->getValue("F"))
- if (Form->getValue()->getAsString() == "Pseudo")
- return false;
-
-
// Ignore "Int_*" and "*_Int" instructions, which are internal aliases.
//
// FIXME: This is a total hack.
diff --git a/utils/TableGen/TGParser.cpp b/utils/TableGen/TGParser.cpp
index 1f4b07b..7bd2fbc 100644
--- a/utils/TableGen/TGParser.cpp
+++ b/utils/TableGen/TGParser.cpp
@@ -812,7 +812,7 @@
case tgtok::XSRA: Code = BinOpInit::SRA; Type = new IntRecTy(); break;
case tgtok::XSRL: Code = BinOpInit::SRL; Type = new IntRecTy(); break;
case tgtok::XSHL: Code = BinOpInit::SHL; Type = new IntRecTy(); break;
- case tgtok::XEq: Code = BinOpInit::EQ; Type = new IntRecTy(); break;
+ case tgtok::XEq: Code = BinOpInit::EQ; Type = new BitRecTy(); break;
case tgtok::XStrConcat:
Code = BinOpInit::STRCONCAT;
Type = new StringRecTy();