Remove extra \n from LLVM_UNREACHABLE calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75416 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMCodeEmitter.cpp b/lib/Target/ARM/ARMCodeEmitter.cpp
index 35502aa..696547d 100644
--- a/lib/Target/ARM/ARMCodeEmitter.cpp
+++ b/lib/Target/ARM/ARMCodeEmitter.cpp
@@ -594,7 +594,7 @@
// We allow inline assembler nodes with empty bodies - they can
// implicitly define registers, which is ok for JIT.
if (MI.getOperand(0).getSymbolName()[0]) {
- llvm_report_error("JIT does not support inline asm!\n");
+ llvm_report_error("JIT does not support inline asm!");
}
break;
}
diff --git a/lib/Target/ARM/ARMJITInfo.cpp b/lib/Target/ARM/ARMJITInfo.cpp
index c9e04c9..a030a8c 100644
--- a/lib/Target/ARM/ARMJITInfo.cpp
+++ b/lib/Target/ARM/ARMJITInfo.cpp
@@ -104,7 +104,7 @@
);
#else // Not an ARM host
void ARMCompilationCallback() {
- LLVM_UNREACHABLE("Cannot call ARMCompilationCallback() on a non-ARM arch!\n");
+ LLVM_UNREACHABLE("Cannot call ARMCompilationCallback() on a non-ARM arch!");
}
#endif
}
diff --git a/lib/Target/IA64/IA64ISelLowering.cpp b/lib/Target/IA64/IA64ISelLowering.cpp
index 094f8c2..8e675eb 100644
--- a/lib/Target/IA64/IA64ISelLowering.cpp
+++ b/lib/Target/IA64/IA64ISelLowering.cpp
@@ -194,7 +194,7 @@
switch (getValueType(I->getType()).getSimpleVT()) {
default:
- LLVM_UNREACHABLE("ERROR in LowerArgs: can't lower this type of arg.\n");
+ LLVM_UNREACHABLE("ERROR in LowerArgs: can't lower this type of arg.");
case MVT::f32:
// fixme? (well, will need to for weird FP structy stuff,
// see intel ABI docs)
@@ -493,7 +493,7 @@
if (InFlag.getNode())
CallOperands.push_back(InFlag);
else
- LLVM_UNREACHABLE("this should never happen!\n");
+ LLVM_UNREACHABLE("this should never happen!");
// to make way for a hack:
Chain = DAG.getNode(IA64ISD::BRCALL, dl, NodeTys,
diff --git a/lib/Target/IA64/IA64InstrInfo.cpp b/lib/Target/IA64/IA64InstrInfo.cpp
index 0537c3e..c76ca32 100644
--- a/lib/Target/IA64/IA64InstrInfo.cpp
+++ b/lib/Target/IA64/IA64InstrInfo.cpp
@@ -129,8 +129,7 @@
} else if (RC == IA64::PRRegisterClass) {
Opc = IA64::ST1;
} else {
- LLVM_UNREACHABLE(
- "sorry, I don't know how to store this sort of reg\n");
+ LLVM_UNREACHABLE("sorry, I don't know how to store this sort of reg");
}
DebugLoc DL = DebugLoc::getUnknownLoc();
@@ -165,7 +164,7 @@
.addReg(IA64::r0);
} else {
LLVM_UNREACHABLE(
- "sorry, I don't know how to load this sort of reg from the stack\n");
+ "sorry, I don't know how to load this sort of reg from the stack");
}
}
@@ -182,7 +181,7 @@
Opc = IA64::LD1;
} else {
LLVM_UNREACHABLE(
- "sorry, I don't know how to load this sort of reg\n");
+ "sorry, I don't know how to load this sort of reg");
}
DebugLoc DL = DebugLoc::getUnknownLoc();
diff --git a/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp b/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp
index b9f1dbd..4d0ee8d 100644
--- a/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp
+++ b/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp
@@ -55,7 +55,7 @@
else if (Subtarget->isTargetELF())
O << ".Lllvm$" << getFunctionNumber() << ".$piclabel";
else
- LLVM_UNREACHABLE( "Don't know how to print PIC label!\n");
+ LLVM_UNREACHABLE( "Don't know how to print PIC label!");
}
/// PrintUnmangledNameSafely - Print out the printable characters in the name.
diff --git a/lib/Target/X86/X86JITInfo.cpp b/lib/Target/X86/X86JITInfo.cpp
index 5b44e4f..4cc27ef 100644
--- a/lib/Target/X86/X86JITInfo.cpp
+++ b/lib/Target/X86/X86JITInfo.cpp
@@ -322,7 +322,7 @@
#else // Not an i386 host
void X86CompilationCallback() {
- LLVM_UNREACHABLE("Cannot call X86CompilationCallback() on a non-x86 arch!\n");
+ LLVM_UNREACHABLE("Cannot call X86CompilationCallback() on a non-x86 arch!");
}
#endif
}
@@ -554,7 +554,7 @@
TLSOffset -= size;
return TLSOffset;
#else
- LLVM_UNREACHABLE("Cannot allocate thread local storage on this arch!\n");
+ LLVM_UNREACHABLE("Cannot allocate thread local storage on this arch!");
return 0;
#endif
}
diff --git a/lib/Target/XCore/XCoreInstrInfo.cpp b/lib/Target/XCore/XCoreInstrInfo.cpp
index 147d29d..ea35504 100644
--- a/lib/Target/XCore/XCoreInstrInfo.cpp
+++ b/lib/Target/XCore/XCoreInstrInfo.cpp
@@ -408,7 +408,7 @@
const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const
{
- LLVM_UNREACHABLE("unimplemented\n");
+ LLVM_UNREACHABLE("unimplemented");
}
void XCoreInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
@@ -428,7 +428,7 @@
const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const
{
- LLVM_UNREACHABLE("unimplemented\n");
+ LLVM_UNREACHABLE("unimplemented");
}
bool XCoreInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
diff --git a/lib/Target/XCore/XCoreRegisterInfo.cpp b/lib/Target/XCore/XCoreRegisterInfo.cpp
index f0ff246..7773064 100644
--- a/lib/Target/XCore/XCoreRegisterInfo.cpp
+++ b/lib/Target/XCore/XCoreRegisterInfo.cpp
@@ -257,7 +257,7 @@
.addReg(ScratchReg, RegState::Kill);
break;
default:
- LLVM_UNREACHABLE("Unexpected Opcode\n");
+ LLVM_UNREACHABLE("Unexpected Opcode");
}
} else {
switch (MI.getOpcode()) {
@@ -278,7 +278,7 @@
.addImm(Offset);
break;
default:
- LLVM_UNREACHABLE("Unexpected Opcode\n");
+ LLVM_UNREACHABLE("Unexpected Opcode");
}
}
} else {
@@ -309,7 +309,7 @@
.addImm(Offset);
break;
default:
- LLVM_UNREACHABLE("Unexpected Opcode\n");
+ LLVM_UNREACHABLE("Unexpected Opcode");
}
}
// Erase old instruction.