diff --git a/utils/TableGen/CodeGenInstruction.cpp b/utils/TableGen/CodeGenInstruction.cpp
index a8f7476..185db01 100644
--- a/utils/TableGen/CodeGenInstruction.cpp
+++ b/utils/TableGen/CodeGenInstruction.cpp
@@ -84,7 +84,7 @@
   isIndirectBranch = R->getValueAsBit("isIndirectBranch");
   isBarrier    = R->getValueAsBit("isBarrier");
   isCall       = R->getValueAsBit("isCall");
-  isSimpleLoad = R->getValueAsBit("isSimpleLoad");
+  canFoldAsLoad = R->getValueAsBit("canFoldAsLoad");
   mayLoad      = R->getValueAsBit("mayLoad");
   mayStore     = R->getValueAsBit("mayStore");
   bool isTwoAddress = R->getValueAsBit("isTwoAddress");
diff --git a/utils/TableGen/CodeGenInstruction.h b/utils/TableGen/CodeGenInstruction.h
index 0727e38..f4afd5e 100644
--- a/utils/TableGen/CodeGenInstruction.h
+++ b/utils/TableGen/CodeGenInstruction.h
@@ -89,7 +89,7 @@
     bool isIndirectBranch;
     bool isBarrier;
     bool isCall;
-    bool isSimpleLoad;
+    bool canFoldAsLoad;
     bool mayLoad, mayStore;
     bool isPredicable;
     bool isConvertibleToThreeAddress;
diff --git a/utils/TableGen/InstrInfoEmitter.cpp b/utils/TableGen/InstrInfoEmitter.cpp
index 705901f..6201690 100644
--- a/utils/TableGen/InstrInfoEmitter.cpp
+++ b/utils/TableGen/InstrInfoEmitter.cpp
@@ -262,7 +262,7 @@
   if (Inst.isBarrier)          OS << "|(1<<TID::Barrier)";
   if (Inst.hasDelaySlot)       OS << "|(1<<TID::DelaySlot)";
   if (Inst.isCall)             OS << "|(1<<TID::Call)";
-  if (Inst.isSimpleLoad)       OS << "|(1<<TID::SimpleLoad)";
+  if (Inst.canFoldAsLoad)      OS << "|(1<<TID::FoldableAsLoad)";
   if (Inst.mayLoad)            OS << "|(1<<TID::MayLoad)";
   if (Inst.mayStore)           OS << "|(1<<TID::MayStore)";
   if (Inst.isPredicable)       OS << "|(1<<TID::Predicable)";