commit 15993f83a419950f06d2879d6701530ae6449317
author Evan Cheng <evan.cheng@apple.com> Mon Jun 27 21:26:13 2011 +0000
committer Evan Cheng <evan.cheng@apple.com> Mon Jun 27 21:26:13 2011 +0000
tree 749e4564ae6f9d1f7c3539ccec1dfd88e1642bc9
parent bea6f615eefae279e53bbb63a31d2c3c67274c45

More refactoring. Move getRegClass from TargetOperandInfo to TargetInstrInfo.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133944 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/ARM/MLxExpansionPass.cpp

diff --git a/lib/Target/ARM/MLxExpansionPass.cpp b/lib/Target/ARM/MLxExpansionPass.cpp
index f6d0242..fc22861 100644
--- a/lib/Target/ARM/MLxExpansionPass.cpp
+++ b/lib/Target/ARM/MLxExpansionPass.cpp
@@ -220,7 +220,7 @@
 
   const TargetInstrDesc &TID1 = TII->get(MulOpc);
   const TargetInstrDesc &TID2 = TII->get(AddSubOpc);
-  unsigned TmpReg = MRI->createVirtualRegister(TID1.getRegClass(0, TRI));
+  unsigned TmpReg = MRI->createVirtualRegister(TII->getRegClass(TID1, 0, TRI));
 
   MachineInstrBuilder MIB = BuildMI(MBB, *MI, MI->getDebugLoc(), TID1, TmpReg)
     .addReg(Src1Reg, getKillRegState(Src1Kill))