commit 15b7a580a79d2e9db8dff2c489181fa3a8d791a1
author Evan Cheng <evan.cheng@apple.com> Mon Jul 27 00:24:36 2009 +0000
committer Evan Cheng <evan.cheng@apple.com> Mon Jul 27 00:24:36 2009 +0000
tree 3602ce5fb311a6cd4f15747473e0dddc1ddab17a
parent 0841e77fe8580b74d80f6432a4f5bfc78a80fd60

Merge isLoadFromStackSlot into one since it behaves the same regardless of sub-target.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77174 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/ARM/ARMBaseInstrInfo.cpp

diff --git a/lib/Target/ARM/ARMBaseInstrInfo.cpp b/lib/Target/ARM/ARMBaseInstrInfo.cpp
index c5e74bf..93ac1d5 100644
--- a/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -491,6 +491,7 @@
   SrcSubIdx = DstSubIdx = 0; // No sub-registers.
 
   switch (MI.getOpcode()) {
+  default: break;
   case ARM::FCPYS:
   case ARM::FCPYD:
   case ARM::VMOVD:
@@ -521,8 +522,10 @@
 unsigned 
 ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
                                       int &FrameIndex) const {
-  unsigned oc = MI->getOpcode();
-  if (oc == getOpcode(ARMII::LDRrr)) {
+  switch (MI->getOpcode()) {
+  default: break;
+  case ARM::LDR:
+  case ARM::t2LDRs:  // FIXME: don't use t2LDRs to access frame.
     if (MI->getOperand(1).isFI() &&
         MI->getOperand(2).isReg() &&
         MI->getOperand(3).isImm() &&
@@ -531,22 +534,25 @@
       FrameIndex = MI->getOperand(1).getIndex();
       return MI->getOperand(0).getReg();
     }
-  }
-  else if (oc == getOpcode(ARMII::LDRri)) {
+    break;
+  case ARM::t2LDRi12:
+  case ARM::tRestore:
     if (MI->getOperand(1).isFI() &&
         MI->getOperand(2).isImm() &&
         MI->getOperand(2).getImm() == 0) {
       FrameIndex = MI->getOperand(1).getIndex();
       return MI->getOperand(0).getReg();
     }
-  }
-  else if (oc == ARM::FLDD || oc == ARM::FLDS) {
+    break;
+  case ARM::FLDD:
+  case ARM::FLDS:
     if (MI->getOperand(1).isFI() &&
         MI->getOperand(2).isImm() &&
         MI->getOperand(2).getImm() == 0) {
       FrameIndex = MI->getOperand(1).getIndex();
       return MI->getOperand(0).getReg();
     }
+    break;
   }
 
   return 0;
@@ -555,8 +561,10 @@
 unsigned
 ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
                                      int &FrameIndex) const {
-  unsigned oc = MI->getOpcode();
-  if (oc == getOpcode(ARMII::STRrr)) {
+  switch (MI->getOpcode()) {
+  default: break;
+  case ARM::STR:
+  case ARM::t2STRs: // FIXME: don't use t2STRs to access frame.
     if (MI->getOperand(1).isFI() &&
         MI->getOperand(2).isReg() &&
         MI->getOperand(3).isImm() &&
@@ -565,22 +573,25 @@
       FrameIndex = MI->getOperand(1).getIndex();
       return MI->getOperand(0).getReg();
     }
-  }
-  else if (oc == getOpcode(ARMII::STRri)) {
+    break;
+  case ARM::t2STRi12:
+  case ARM::tSpill:
     if (MI->getOperand(1).isFI() &&
         MI->getOperand(2).isImm() &&
         MI->getOperand(2).getImm() == 0) {
       FrameIndex = MI->getOperand(1).getIndex();
       return MI->getOperand(0).getReg();
     }
-  }
-  else if (oc == ARM::FSTD || oc == ARM::FSTS) {
+    break;
+  case ARM::FSTD:
+  case  ARM::FSTS:
     if (MI->getOperand(1).isFI() &&
         MI->getOperand(2).isImm() &&
         MI->getOperand(2).getImm() == 0) {
       FrameIndex = MI->getOperand(1).getIndex();
       return MI->getOperand(0).getReg();
     }
+    break;
   }
 
   return 0;