Add a big assert making sure 2 address instructions are formed right
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5057 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/RegAllocSimple.cpp b/lib/CodeGen/RegAllocSimple.cpp
index 97b42b0..17b1044 100644
--- a/lib/CodeGen/RegAllocSimple.cpp
+++ b/lib/CodeGen/RegAllocSimple.cpp
@@ -379,6 +379,12 @@
if (TM.getInstrInfo().isTwoAddrInstr(MI->getOpcode()) && i == 0) {
// must be same register number as the first operand
// This maps a = b + c into b += c, and saves b into a's spot
+ assert(MI->getOperand(1).isRegister() &&
+ MI->getOperand(1).getAllocatedRegNum() &&
+ MF->getRegClass(virtualReg) ==
+ PhysRegClasses[MI->getOperand(1).getAllocatedRegNum()] &&
+ "Two address instruction invalid!");
+
physReg = MI->getOperand(1).getAllocatedRegNum();
} else {
physReg = getFreeReg(virtualReg);