Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand 3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142105 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/utils/TableGen/X86RecognizableInstr.h b/utils/TableGen/X86RecognizableInstr.h
index 4441597..7ed820b 100644
--- a/utils/TableGen/X86RecognizableInstr.h
+++ b/utils/TableGen/X86RecognizableInstr.h
@@ -70,7 +70,9 @@
bool Is64Bit;
// Whether the instruction has the predicate "In32BitMode"
bool Is32Bit;
-
+ // Whether the instruction is BEXTR
+ bool IsBEXTR;
+
/// The instruction name as listed in the tables
std::string Name;
/// The AT&T AsmString for the instruction