commit 1858786285139b87961d9ca08de91dcd59364afb
author Akira Hatanaka <ahatanaka@mips.com> Tue Aug 06 23:08:38 2013 +0000
committer Akira Hatanaka <ahatanaka@mips.com> Tue Aug 06 23:08:38 2013 +0000
tree 2e0913c83c690b1c3d8e2e0604b0681e3b2d15a1
parent 3492eefa4b2509c87598678a6977074a3f6a50e6

[mips] Rename register classes CPURegs and CPU64Regs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187832 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/Mips/MipsSEInstrInfo.cpp

diff --git a/lib/Target/Mips/MipsSEInstrInfo.cpp b/lib/Target/Mips/MipsSEInstrInfo.cpp
index ca96772..9521043 100644
--- a/lib/Target/Mips/MipsSEInstrInfo.cpp
+++ b/lib/Target/Mips/MipsSEInstrInfo.cpp
@@ -94,8 +94,8 @@
                                   bool KillSrc) const {
   unsigned Opc = 0, ZeroReg = 0;
 
-  if (Mips::CPURegsRegClass.contains(DestReg)) { // Copy to CPU Reg.
-    if (Mips::CPURegsRegClass.contains(SrcReg))
+  if (Mips::GPR32RegClass.contains(DestReg)) { // Copy to CPU Reg.
+    if (Mips::GPR32RegClass.contains(SrcReg))
       Opc = Mips::ADDu, ZeroReg = Mips::ZERO;
     else if (Mips::CCRRegClass.contains(SrcReg))
       Opc = Mips::CFC1;
@@ -115,7 +115,7 @@
       return;
     }
   }
-  else if (Mips::CPURegsRegClass.contains(SrcReg)) { // Copy from CPU Reg.
+  else if (Mips::GPR32RegClass.contains(SrcReg)) { // Copy from CPU Reg.
     if (Mips::CCRRegClass.contains(DestReg))
       Opc = Mips::CTC1;
     else if (Mips::FGR32RegClass.contains(DestReg))
@@ -141,8 +141,8 @@
     Opc = Mips::FMOV_D32;
   else if (Mips::FGR64RegClass.contains(DestReg, SrcReg))
     Opc = Mips::FMOV_D64;
-  else if (Mips::CPU64RegsRegClass.contains(DestReg)) { // Copy to CPU64 Reg.
-    if (Mips::CPU64RegsRegClass.contains(SrcReg))
+  else if (Mips::GPR64RegClass.contains(DestReg)) { // Copy to CPU64 Reg.
+    if (Mips::GPR64RegClass.contains(SrcReg))
       Opc = Mips::DADDu, ZeroReg = Mips::ZERO_64;
     else if (Mips::HIRegs64RegClass.contains(SrcReg))
       Opc = Mips::MFHI64, SrcReg = 0;
@@ -151,7 +151,7 @@
     else if (Mips::FGR64RegClass.contains(SrcReg))
       Opc = Mips::DMFC1;
   }
-  else if (Mips::CPU64RegsRegClass.contains(SrcReg)) { // Copy from CPU64 Reg.
+  else if (Mips::GPR64RegClass.contains(SrcReg)) { // Copy from CPU64 Reg.
     if (Mips::HIRegs64RegClass.contains(DestReg))
       Opc = Mips::MTHI64, DestReg = 0;
     else if (Mips::LORegs64RegClass.contains(DestReg))
@@ -185,9 +185,9 @@
 
   unsigned Opc = 0;
 
-  if (Mips::CPURegsRegClass.hasSubClassEq(RC))
+  if (Mips::GPR32RegClass.hasSubClassEq(RC))
     Opc = IsN64 ? Mips::SW_P8 : Mips::SW;
-  else if (Mips::CPU64RegsRegClass.hasSubClassEq(RC))
+  else if (Mips::GPR64RegClass.hasSubClassEq(RC))
     Opc = IsN64 ? Mips::SD_P8 : Mips::SD;
   else if (Mips::ACRegsRegClass.hasSubClassEq(RC))
     Opc = IsN64 ? Mips::STORE_AC64_P8 : Mips::STORE_AC64;
@@ -218,9 +218,9 @@
   MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad);
   unsigned Opc = 0;
 
-  if (Mips::CPURegsRegClass.hasSubClassEq(RC))
+  if (Mips::GPR32RegClass.hasSubClassEq(RC))
     Opc = IsN64 ? Mips::LW_P8 : Mips::LW;
-  else if (Mips::CPU64RegsRegClass.hasSubClassEq(RC))
+  else if (Mips::GPR64RegClass.hasSubClassEq(RC))
     Opc = IsN64 ? Mips::LD_P8 : Mips::LD;
   else if (Mips::ACRegsRegClass.hasSubClassEq(RC))
     Opc = IsN64 ? Mips::LOAD_AC64_P8 : Mips::LOAD_AC64;
@@ -340,7 +340,7 @@
   unsigned LUi = STI.isABI_N64() ? Mips::LUi64 : Mips::LUi;
   unsigned ZEROReg = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
   const TargetRegisterClass *RC = STI.isABI_N64() ?
-    &Mips::CPU64RegsRegClass : &Mips::CPURegsRegClass;
+    &Mips::GPR64RegClass : &Mips::GPR32RegClass;
   bool LastInstrIsADDiu = NewImm;
 
   const MipsAnalyzeImmediate::InstSeq &Seq =