Remove the '-disable-scheduling' flag and replace it with the 'source' option of
the '-pre-RA-sched' flag. It actually makes more sense to do it this way. Also,
keep track of the SDNode ordering by default. Eventually, we would like to make
this ordering a way to break a "tie" in the scheduler. However, doing that now
breaks the "CodeGen/X86/abi-isel.ll" test for 32-bit Linux.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94308 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 67b6d5c..f1b6f1e 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -593,7 +593,7 @@
NodeAllocator.Deallocate(AllNodes.remove(N));
// Remove the ordering of this node.
- if (Ordering) Ordering->remove(N);
+ Ordering->remove(N);
}
/// RemoveNodeFromCSEMaps - Take the specified node out of the CSE map that
@@ -790,8 +790,7 @@
getVTList(MVT::Other)),
Root(getEntryNode()), Ordering(0) {
AllNodes.push_back(&EntryNode);
- if (DisableScheduling)
- Ordering = new SDNodeOrdering();
+ Ordering = new SDNodeOrdering();
}
void SelectionDAG::init(MachineFunction &mf, MachineModuleInfo *mmi,
@@ -830,8 +829,7 @@
EntryNode.UseList = 0;
AllNodes.push_back(&EntryNode);
Root = getEntryNode();
- if (DisableScheduling)
- Ordering = new SDNodeOrdering();
+ Ordering = new SDNodeOrdering();
}
SDValue SelectionDAG::getSExtOrTrunc(SDValue Op, DebugLoc DL, EVT VT) {
@@ -5241,14 +5239,13 @@
/// AssignOrdering - Assign an order to the SDNode.
void SelectionDAG::AssignOrdering(SDNode *SD, unsigned Order) {
assert(SD && "Trying to assign an order to a null node!");
- if (Ordering)
- Ordering->add(SD, Order);
+ Ordering->add(SD, Order);
}
/// GetOrdering - Get the order for the SDNode.
unsigned SelectionDAG::GetOrdering(const SDNode *SD) const {
assert(SD && "Trying to get the order of a null node!");
- return Ordering ? Ordering->getOrder(SD) : 0;
+ return Ordering->getOrder(SD);
}