Add new ImplicitDef node, rename CopyRegSDNode class to RegSDNode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19535 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index 58f9889..c735faa 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -244,6 +244,11 @@
assert(getTypeAction(Node->getValueType(0)) == Legal &&
"This must be legal!");
break;
+ case ISD::ImplicitDef:
+ Tmp1 = LegalizeOp(Node->getOperand(0));
+ if (Tmp1 != Node->getOperand(0))
+ Result = DAG.getImplicitDef(cast<RegSDNode>(Node)->getReg());
+ break;
case ISD::Constant:
// We know we don't need to expand constants here, constants only have one
// value and we check that it is fine above.
@@ -398,13 +403,12 @@
// Legalize the incoming value (must be legal).
Tmp2 = LegalizeOp(Node->getOperand(1));
if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
- Result = DAG.getCopyToReg(Tmp1, Tmp2,
- cast<CopyRegSDNode>(Node)->getReg());
+ Result = DAG.getCopyToReg(Tmp1, Tmp2, cast<RegSDNode>(Node)->getReg());
break;
case Expand: {
SDOperand Lo, Hi;
ExpandOp(Node->getOperand(1), Lo, Hi);
- unsigned Reg = cast<CopyRegSDNode>(Node)->getReg();
+ unsigned Reg = cast<RegSDNode>(Node)->getReg();
Result = DAG.getCopyToReg(Tmp1, Lo, Reg);
Result = DAG.getCopyToReg(Result, Hi, Reg+1);
assert(isTypeLegal(Result.getValueType()) &&
@@ -748,7 +752,7 @@
}
case ISD::CopyFromReg: {
- unsigned Reg = cast<CopyRegSDNode>(Node)->getReg();
+ unsigned Reg = cast<RegSDNode>(Node)->getReg();
// Aggregate register values are always in consequtive pairs.
Lo = DAG.getCopyFromReg(Reg, NVT);
Hi = DAG.getCopyFromReg(Reg+1, NVT);
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 2f5fdc3..ecb9151 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -880,6 +880,7 @@
case ISD::ConstantPool: return "ConstantPoolIndex";
case ISD::CopyToReg: return "CopyToReg";
case ISD::CopyFromReg: return "CopyFromReg";
+ case ISD::ImplicitDef: return "ImplicitDef";
case ISD::ADD: return "add";
case ISD::SUB: return "sub";
@@ -1006,7 +1007,7 @@
if (LBB)
std::cerr << LBB->getName() << " ";
std::cerr << (const void*)BBDN->getBasicBlock() << ">";
- } else if (const CopyRegSDNode *C2V = dyn_cast<CopyRegSDNode>(this)) {
+ } else if (const RegSDNode *C2V = dyn_cast<RegSDNode>(this)) {
std::cerr << "<reg #" << C2V->getReg() << ">";
} else if (const ExternalSymbolSDNode *ES =
dyn_cast<ExternalSymbolSDNode>(this)) {
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 6a81975..ed363e1 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -772,8 +772,9 @@
CopyValueToVirtualRegister(SelectionDAGLowering &SDL, Value *V, unsigned Reg) {
SelectionDAG &DAG = SDL.DAG;
SDOperand Op = SDL.getValue(V);
- if (CopyRegSDNode *CR = dyn_cast<CopyRegSDNode>(Op))
- assert(CR->getReg() != Reg && "Copy from a reg to the same reg!");
+ assert((Op.getOpcode() != ISD::CopyFromReg ||
+ cast<RegSDNode>(Op)->getReg() != Reg) &&
+ "Copy from a reg to the same reg!");
return DAG.getCopyToReg(DAG.getRoot(), Op, Reg);
}
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
index 49568ee..f398568 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
@@ -85,7 +85,7 @@
if (LBB)
Op += LBB->getName();
//Op += " " + (const void*)BBDN->getBasicBlock();
- } else if (const CopyRegSDNode *C2V = dyn_cast<CopyRegSDNode>(Node)) {
+ } else if (const RegSDNode *C2V = dyn_cast<RegSDNode>(Node)) {
Op += " #" + utostr(C2V->getReg());
} else if (const ExternalSymbolSDNode *ES =
dyn_cast<ExternalSymbolSDNode>(Node)) {