rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45667 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMInstrThumb.td b/lib/Target/ARM/ARMInstrThumb.td
index 2782f7d..c8ed735 100644
--- a/lib/Target/ARM/ARMInstrThumb.td
+++ b/lib/Target/ARM/ARMInstrThumb.td
@@ -188,7 +188,7 @@
}
// FIXME: remove when we have a way to marking a MI with these properties.
-let isLoad = 1, isReturn = 1, isTerminator = 1 in
+let isSimpleLoad = 1, isReturn = 1, isTerminator = 1 in
def tPOP_RET : TI<(outs reglist:$dst1, variable_ops), (ins),
"pop $dst1", []>;
@@ -237,7 +237,7 @@
// Load Store Instructions.
//
-let isLoad = 1 in {
+let isSimpleLoad = 1 in {
def tLDR : TI4<(outs GPR:$dst), (ins t_addrmode_s4:$addr),
"ldr $dst, $addr",
[(set GPR:$dst, (load t_addrmode_s4:$addr))]>;
@@ -276,7 +276,7 @@
let isReMaterializable = 1 in
def tLDRcp : TIs<(outs GPR:$dst), (ins i32imm:$addr),
"ldr $dst, $addr", []>;
-} // isLoad
+} // isSimpleLoad
def tSTR : TI4<(outs), (ins GPR:$src, t_addrmode_s4:$addr),
"str $src, $addr",
@@ -307,7 +307,7 @@
// TODO: A7-44: LDMIA - load multiple
-let isLoad = 1 in
+let isSimpleLoad = 1 in
def tPOP : TI<(outs reglist:$dst1, variable_ops), (ins),
"pop $dst1", []>;