commit 1b91bcddd5a26c8bfad7cc1195aa092d42053c0e
author Justin Holewinski <justin.holewinski@gmail.com> Thu Jun 16 17:49:58 2011 +0000
committer Justin Holewinski <justin.holewinski@gmail.com> Thu Jun 16 17:49:58 2011 +0000
tree 0f09f0dcda72e1803ef7467a59082c88d55a1b87
parent 79c890f64f3b67f9b11341aa452c4302b75184aa

PTX: Rename register classes for readability and combine int and fp registers

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133171 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/PTX/PTXISelLowering.cpp

diff --git a/lib/Target/PTX/PTXISelLowering.cpp b/lib/Target/PTX/PTXISelLowering.cpp
index 622e542..cacd5c8 100644
--- a/lib/Target/PTX/PTXISelLowering.cpp
+++ b/lib/Target/PTX/PTXISelLowering.cpp
@@ -27,12 +27,12 @@
 PTXTargetLowering::PTXTargetLowering(TargetMachine &TM)
   : TargetLowering(TM, new TargetLoweringObjectFileELF()) {
   // Set up the register classes.
-  addRegisterClass(MVT::i1,  PTX::PredsRegisterClass);
-  addRegisterClass(MVT::i16, PTX::RRegu16RegisterClass);
-  addRegisterClass(MVT::i32, PTX::RRegu32RegisterClass);
-  addRegisterClass(MVT::i64, PTX::RRegu64RegisterClass);
-  addRegisterClass(MVT::f32, PTX::RRegf32RegisterClass);
-  addRegisterClass(MVT::f64, PTX::RRegf64RegisterClass);
+  addRegisterClass(MVT::i1,  PTX::RegPredRegisterClass);
+  addRegisterClass(MVT::i16, PTX::RegI16RegisterClass);
+  addRegisterClass(MVT::i32, PTX::RegI32RegisterClass);
+  addRegisterClass(MVT::i64, PTX::RegI64RegisterClass);
+  addRegisterClass(MVT::f32, PTX::RegF32RegisterClass);
+  addRegisterClass(MVT::f64, PTX::RegF64RegisterClass);
 
   setBooleanContents(ZeroOrOneBooleanContent);
 
@@ -63,7 +63,7 @@
   setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
   setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
 
-  // need to lower SETCC of Preds into bitwise logic
+  // need to lower SETCC of RegPred into bitwise logic
   setOperationAction(ISD::SETCC, MVT::i1, Custom);
 
   setMinFunctionAlignment(2);
@@ -161,12 +161,12 @@
   void reset() { loc = RC->begin(); }
   bool operator==(MVT::SimpleValueType _VT) const { return VT == _VT; }
 } argmap[] = {
-  argmap_entry(MVT::i1,  PTX::PredsRegisterClass),
-  argmap_entry(MVT::i16, PTX::RRegu16RegisterClass),
-  argmap_entry(MVT::i32, PTX::RRegu32RegisterClass),
-  argmap_entry(MVT::i64, PTX::RRegu64RegisterClass),
-  argmap_entry(MVT::f32, PTX::RRegf32RegisterClass),
-  argmap_entry(MVT::f64, PTX::RRegf64RegisterClass)
+  argmap_entry(MVT::i1,  PTX::RegPredRegisterClass),
+  argmap_entry(MVT::i16, PTX::RegI16RegisterClass),
+  argmap_entry(MVT::i32, PTX::RegI32RegisterClass),
+  argmap_entry(MVT::i64, PTX::RegI64RegisterClass),
+  argmap_entry(MVT::f32, PTX::RegF32RegisterClass),
+  argmap_entry(MVT::f64, PTX::RegF64RegisterClass)
 };
 }                               // end anonymous namespace
 
@@ -212,7 +212,7 @@
     if (entry == argmap + array_lengthof(argmap))
       llvm_unreachable("Type of argument is not supported");
 
-    if (MFI->isKernel() && entry->RC == PTX::PredsRegisterClass)
+    if (MFI->isKernel() && entry->RC == PTX::RegPredRegisterClass)
       llvm_unreachable("cannot pass preds to kernel");
 
     MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
@@ -277,11 +277,11 @@
     reg = PTX::RD0;
   }
   else if (Outs[0].VT == MVT::f32) {
-    reg = PTX::F0;
+    reg = PTX::R0;
   }
   else {
     assert(Outs[0].VT == MVT::f64 && "Can return only basic types");
-    reg = PTX::FD0;
+    reg = PTX::RD0;
   }
 
   MachineFunction &MF = DAG.getMachineFunction();