Do not use MachineOperand::isVirtualRegister either!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11283 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/LiveIntervalAnalysis.cpp b/lib/CodeGen/LiveIntervalAnalysis.cpp
index 7b70814..caa9e2e 100644
--- a/lib/CodeGen/LiveIntervalAnalysis.cpp
+++ b/lib/CodeGen/LiveIntervalAnalysis.cpp
@@ -115,7 +115,8 @@
for (int i = mi->getNumOperands() - 1; i >= 0; --i) {
MachineOperand& mop = mi->getOperand(i);
- if (mop.isVirtualRegister()) {
+ if (mop.isRegister() &&
+ MRegisterInfo::isVirtualRegister(mop.getReg())) {
unsigned reg = mop.getAllocatedRegNum();
Reg2IntervalMap::iterator r2iit = r2iMap_.find(reg);
assert(r2iit != r2iMap_.end());
diff --git a/lib/CodeGen/LiveVariables.cpp b/lib/CodeGen/LiveVariables.cpp
index 28b5f1e..be4f546 100644
--- a/lib/CodeGen/LiveVariables.cpp
+++ b/lib/CodeGen/LiveVariables.cpp
@@ -231,11 +231,10 @@
// Process all explicit uses...
for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
MachineOperand &MO = MI->getOperand(i);
- if (MO.isUse()) {
- if (MO.isVirtualRegister() && !MO.getVRegValueOrNull()) {
+ if (MO.isUse() && MO.isRegister()) {
+ if (MRegisterInfo::isVirtualRegister(MO.getReg())){
HandleVirtRegUse(getVarInfo(MO.getReg()), MBB, MI);
- } else if (MO.isRegister() &&
- MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
+ } else if (MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
AllocatablePhysicalRegisters[MO.getReg()]) {
HandlePhysRegUse(MO.getReg(), MI);
}
@@ -250,16 +249,15 @@
// Process all explicit defs...
for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
MachineOperand &MO = MI->getOperand(i);
- if (MO.isDef()) {
- if (MO.isVirtualRegister()) {
+ if (MO.isDef() && MO.isRegister()) {
+ if (MRegisterInfo::isVirtualRegister(MO.getReg())) {
VarInfo &VRInfo = getVarInfo(MO.getReg());
assert(VRInfo.DefBlock == 0 && "Variable multiply defined!");
VRInfo.DefBlock = MBB; // Created here...
VRInfo.DefInst = MI;
VRInfo.Kills.push_back(std::make_pair(MBB, MI)); // Defaults to dead
- } else if (MO.isRegister() &&
- MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
+ } else if (MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
AllocatablePhysicalRegisters[MO.getReg()]) {
HandlePhysRegDef(MO.getReg(), MI);
}
diff --git a/lib/CodeGen/PHIElimination.cpp b/lib/CodeGen/PHIElimination.cpp
index 4d34080..afb87e5 100644
--- a/lib/CodeGen/PHIElimination.cpp
+++ b/lib/CodeGen/PHIElimination.cpp
@@ -73,7 +73,7 @@
// Unlink the PHI node from the basic block... but don't delete the PHI yet
MBB.erase(MBB.begin());
- assert(MI->getOperand(0).isVirtualRegister() &&
+ assert(MRegisterInfo::isVirtualRegister(MI->getOperand(0).getReg()) &&
"PHI node doesn't write virt reg?");
unsigned DestReg = MI->getOperand(0).getAllocatedRegNum();
@@ -174,7 +174,7 @@
MachineInstr *PrevInst = *(I-1);
for (unsigned i = 0, e = PrevInst->getNumOperands(); i != e; ++i) {
MachineOperand &MO = PrevInst->getOperand(i);
- if (MO.isVirtualRegister() && MO.getReg() == IncomingReg)
+ if (MO.isRegister() && MO.getReg() == IncomingReg)
if (MO.isDef()) {
HaveNotEmitted = false;
break;
@@ -183,7 +183,7 @@
}
if (HaveNotEmitted) { // If the copy has not already been emitted, do it.
- assert(opVal.isVirtualRegister() &&
+ assert(MRegisterInfo::isVirtualRegister(opVal.getReg()) &&
"Machine PHI Operands must all be virtual registers!");
unsigned SrcReg = opVal.getReg();
RegInfo->copyRegToReg(opBlock, I, IncomingReg, SrcReg, RC);
diff --git a/lib/CodeGen/PrologEpilogInserter.cpp b/lib/CodeGen/PrologEpilogInserter.cpp
index b44e386..79406f9 100644
--- a/lib/CodeGen/PrologEpilogInserter.cpp
+++ b/lib/CodeGen/PrologEpilogInserter.cpp
@@ -116,12 +116,12 @@
} else {
for (unsigned i = 0, e = (*I)->getNumOperands(); i != e; ++i) {
MachineOperand &MO = (*I)->getOperand(i);
- assert(!MO.isVirtualRegister() &&
- "Register allocation must be performed!");
- if (MO.isRegister() && MO.isDef() &&
- MRegisterInfo::isPhysicalRegister(MO.getReg()))
+ if (MO.isRegister() && MO.isDef()) {
+ assert(MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
+ "Register allocation must be performed!");
ModifiedRegs[MO.getReg()] = true; // Register is modified
- }
+ }
+ }
++I;
}
diff --git a/lib/CodeGen/RegAllocLinearScan.cpp b/lib/CodeGen/RegAllocLinearScan.cpp
index 42b8ae3..9df824a 100644
--- a/lib/CodeGen/RegAllocLinearScan.cpp
+++ b/lib/CodeGen/RegAllocLinearScan.cpp
@@ -405,8 +405,9 @@
for (unsigned i = 0, e = (*currentInstr_)->getNumOperands();
i != e; ++i) {
MachineOperand& op = (*currentInstr_)->getOperand(i);
- if (op.isVirtualRegister()) {
- unsigned virtReg = op.getAllocatedRegNum();
+ if (op.isRegister() &&
+ MRegisterInfo::isVirtualRegister(op.getReg())) {
+ unsigned virtReg = op.getReg();
Virt2PhysMap::const_iterator it = v2pMap_.find(virtReg);
if (it != v2pMap_.end()) {
DEBUG(std::cerr << "\t\t\t%reg" << it->first
@@ -441,7 +442,8 @@
"registers:\n");
for (unsigned i = 0; i != numOperands; ++i) {
MachineOperand& op = (*currentInstr_)->getOperand(i);
- if (op.isVirtualRegister() && op.isUse()) {
+ if (op.isRegister() && op.isUse() &&
+ MRegisterInfo::isVirtualRegister(op.getReg())) {
unsigned virtReg = op.getAllocatedRegNum();
unsigned physReg = 0;
Virt2PhysMap::iterator it = v2pMap_.find(virtReg);
@@ -471,9 +473,10 @@
"registers:\n");
for (unsigned i = 0; i != numOperands; ++i) {
MachineOperand& op = (*currentInstr_)->getOperand(i);
- if (op.isVirtualRegister()) {
+ if (op.isRegister() &&
+ MRegisterInfo::isVirtualRegister(op.getReg())) {
assert(!op.isUse() && "we should not have uses here!");
- unsigned virtReg = op.getAllocatedRegNum();
+ unsigned virtReg = op.getReg();
unsigned physReg = 0;
Virt2PhysMap::iterator it = v2pMap_.find(virtReg);
if (it != v2pMap_.end()) {
diff --git a/lib/CodeGen/RegAllocLocal.cpp b/lib/CodeGen/RegAllocLocal.cpp
index 23ec845..3f53106 100644
--- a/lib/CodeGen/RegAllocLocal.cpp
+++ b/lib/CodeGen/RegAllocLocal.cpp
@@ -522,8 +522,8 @@
//
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
if (MI->getOperand(i).isUse() &&
- !MI->getOperand(i).isDef() &&
- MI->getOperand(i).isVirtualRegister()){
+ !MI->getOperand(i).isDef() && MI->getOperand(i).isRegister() &&
+ MRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg())) {
unsigned VirtSrcReg = MI->getOperand(i).getAllocatedRegNum();
unsigned PhysSrcReg = reloadVirtReg(MBB, I, VirtSrcReg);
MI->SetMachineOperandReg(i, PhysSrcReg); // Assign the input register
@@ -589,8 +589,8 @@
// we need to scavenge a register.
//
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
- if (MI->getOperand(i).isDef() &&
- MI->getOperand(i).isVirtualRegister()) {
+ if (MI->getOperand(i).isDef() && MI->getOperand(i).isRegister() &&
+ MRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg())) {
unsigned DestVirtReg = MI->getOperand(i).getAllocatedRegNum();
unsigned DestPhysReg;
diff --git a/lib/CodeGen/RegAllocSimple.cpp b/lib/CodeGen/RegAllocSimple.cpp
index 44f37c6..ac76220 100644
--- a/lib/CodeGen/RegAllocSimple.cpp
+++ b/lib/CodeGen/RegAllocSimple.cpp
@@ -174,7 +174,7 @@
for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
MachineOperand &op = MI->getOperand(i);
- if (op.isVirtualRegister()) {
+ if (op.isRegister() && MRegisterInfo::isVirtualRegister(op.getReg())) {
unsigned virtualReg = (unsigned) op.getAllocatedRegNum();
DEBUG(std::cerr << "op: " << op << "\n");
DEBUG(std::cerr << "\t inst[" << i << "]: ";