commit 1d9d7427c4a4e3c7bdcfd1f725447f355e509c20
author Nate Begeman <natebegeman@mac.com> Tue Oct 18 00:28:58 2005 +0000
committer Nate Begeman <natebegeman@mac.com> Tue Oct 18 00:28:58 2005 +0000
tree 67e012c546bbb580f87a99504c8c05bb63f0ae54
parent a0e221dc75ee1f2d8830eec9569116386a56a936

First bits of 64 bit PowerPC stuff, currently disabled.  A lot of this is
purely mechanical.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23778 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/PowerPC/PPCInstrInfo.cpp

diff --git a/lib/Target/PowerPC/PPCInstrInfo.cpp b/lib/Target/PowerPC/PPCInstrInfo.cpp
index 2f76659..cfeda7b 100644
--- a/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -25,7 +25,7 @@
                                unsigned& sourceReg,
                                unsigned& destReg) const {
   MachineOpCode oc = MI.getOpcode();
-  if (oc == PPC::OR) {                      // or r1, r2, r2
+  if (oc == PPC::OR4 || oc == PPC::OR8) {                      // or r1, r2, r2
     assert(MI.getNumOperands() == 3 &&
            MI.getOperand(0).isRegister() &&
            MI.getOperand(1).isRegister() &&