commit 1de588df69ceb999dd4680679cc3fe519bf9a124
author Jim Grosbach <grosbach@apple.com> Thu Oct 14 18:54:27 2010 +0000
committer Jim Grosbach <grosbach@apple.com> Thu Oct 14 18:54:27 2010 +0000
tree f76612bb9fc2dd4ac0d6b544639fb5ed8e81ad5b
parent ab00e9f498a23a511a06d9fcd33e7232e9a3f916

MOVi16 and MOVT ARM mode encodings.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116498 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/ARM/ARMInstrInfo.td

diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index 55f7a37..8fc5c3c 100644
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -1634,6 +1634,8 @@
 def MOVs : AsI1<0b1101, (outs GPR:$Rd), (ins so_reg:$src),
                 DPSoRegFrm, IIC_iMOVsr,
                 "mov", "\t$Rd, $src", [(set GPR:$Rd, so_reg:$src)]>, UnaryDP {
+  bits<12> src;
+  let Inst{11-0} = src;
   let Inst{25} = 0;
 }
 
@@ -1649,23 +1651,33 @@
 }
 
 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
-def MOVi16 : AI1<0b1000, (outs GPR:$dst), (ins i32imm:$src),
+def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins i32imm:$imm),
                  DPFrm, IIC_iMOVi,
-                 "movw", "\t$dst, $src",
-                 [(set GPR:$dst, imm0_65535:$src)]>,
+                 "movw", "\t$Rd, $imm",
+                 [(set GPR:$Rd, imm0_65535:$imm)]>,
                  Requires<[IsARM, HasV6T2]>, UnaryDP {
+  bits<4> Rd;
+  bits<16> imm;
+  let Inst{15-12} = Rd;
+  let Inst{11-0}  = imm{11-0};
+  let Inst{19-16} = imm{15-12};
   let Inst{20} = 0;
   let Inst{25} = 1;
 }
 
-let Constraints = "$src = $dst" in
-def MOVTi16 : AI1<0b1010, (outs GPR:$dst), (ins GPR:$src, i32imm:$imm),
+let Constraints = "$src = $Rd" in
+def MOVTi16 : AI1<0b1010, (outs GPR:$Rd), (ins GPR:$src, i32imm:$imm),
                   DPFrm, IIC_iMOVi,
-                  "movt", "\t$dst, $imm",
-                  [(set GPR:$dst,
+                  "movt", "\t$Rd, $imm",
+                  [(set GPR:$Rd,
                         (or (and GPR:$src, 0xffff),
                             lo16AllZero:$imm))]>, UnaryDP,
                   Requires<[IsARM, HasV6T2]> {
+  bits<4> Rd;
+  bits<16> imm;
+  let Inst{15-12} = Rd;
+  let Inst{11-0}  = imm{11-0};
+  let Inst{19-16} = imm{15-12};
   let Inst{20} = 0;
   let Inst{25} = 1;
 }

test/MC/ARM/simple-encoding.ll

diff --git a/test/MC/ARM/simple-encoding.ll b/test/MC/ARM/simple-encoding.ll
index 05ecb96..a165160 100644
--- a/test/MC/ARM/simple-encoding.ll
+++ b/test/MC/ARM/simple-encoding.ll
@@ -74,4 +74,21 @@
   ret i32 %add
 }
 
+define i32 @f8(i32 %a) nounwind readnone ssp {
+entry:
+; CHECK: f8
+; CHECK: movt r0, #42405              @ encoding: [0xa5,0x05,0x4a,0xe3]
+  %and = and i32 %a, 65535
+  %or = or i32 %and, -1515913216
+  ret i32 %or
+}
+
+define i32 @f9() nounwind readnone ssp {
+entry:
+; CHECK: f9
+; CHECK: movw r0, #42405              @ encoding: [0xa5,0x05,0x0a,0xe3]
+  ret i32 42405
+}
+
+
 declare void @llvm.trap() nounwind