| commit | 1deef27b0ad538e5017675cf1e085002973bbbb2 | [log] [tgz] |
|---|---|---|
| author | Evan Cheng <evan.cheng@apple.com> | Thu Apr 29 00:59:34 2010 +0000 |
| committer | Evan Cheng <evan.cheng@apple.com> | Thu Apr 29 00:59:34 2010 +0000 |
| tree | c83d623e254d159558ae125c196b0a2f69bca488 | |
| parent | 6691a8935c9f2e049ff5eed45ba2894f60108909 [diff] [blame] |
Check Reg against zero. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102573 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp index 43e6b1b..254a654 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -3699,7 +3699,7 @@ unsigned Reg = 0; if (N.getOpcode() == ISD::CopyFromReg) { Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg(); - if (TargetRegisterInfo::isVirtualRegister(Reg)) { + if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) { MachineRegisterInfo &RegInfo = MF.getRegInfo(); unsigned PR = RegInfo.getLiveInPhysReg(Reg); if (PR)