Add code enough for emission of reg-reg and reg-imm moves. This allows us to compile "ret i16 0" properly!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70710 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/MSP430/MSP430ISelLowering.cpp b/lib/Target/MSP430/MSP430ISelLowering.cpp
index 7577a53..c4b3993 100644
--- a/lib/Target/MSP430/MSP430ISelLowering.cpp
+++ b/lib/Target/MSP430/MSP430ISelLowering.cpp
@@ -39,7 +39,7 @@
TargetLowering(tm), Subtarget(*tm.getSubtargetImpl()), TM(tm) {
// Set up the register classes.
- addRegisterClass(MVT::i16, MSP430::MSP430RegsRegisterClass);
+ addRegisterClass(MVT::i16, MSP430::GR16RegisterClass);
// Compute derived properties from the register classes
computeRegisterProperties();
@@ -111,7 +111,7 @@
abort();
case MVT::i16:
unsigned VReg =
- RegInfo.createVirtualRegister(MSP430::MSP430RegsRegisterClass);
+ RegInfo.createVirtualRegister(MSP430::GR16RegisterClass);
RegInfo.addLiveIn(VA.getLocReg(), VReg);
SDValue ArgValue = DAG.getCopyFromReg(Root, dl, VReg, RegVT);