ISD::ADDE / ISD::SUBE updates the carry bit so they should isle to ADCS and SBCS / RSCS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74200 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/test/CodeGen/ARM/carry.ll b/test/CodeGen/ARM/carry.ll
new file mode 100644
index 0000000..82a5693
--- /dev/null
+++ b/test/CodeGen/ARM/carry.ll
@@ -0,0 +1,16 @@
+; RUN: llvm-as < %s | llc -march=arm | grep "subs r" | count 2
+; RUN: llvm-as < %s | llc -march=arm | grep adc
+; RUN: llvm-as < %s | llc -march=arm | grep sbc
+
+define i64 @f1(i64 %a, i64 %b) {
+entry:
+ %tmp = sub i64 %a, %b
+ ret i64 %tmp
+}
+
+define i64 @f2(i64 %a, i64 %b) {
+entry:
+ %tmp1 = shl i64 %a, 1
+ %tmp2 = sub i64 %tmp1, %b
+ ret i64 %tmp2
+}