Relex assertions to account for additional implicit def / use operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36430 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMInstrInfo.cpp b/lib/Target/ARM/ARMInstrInfo.cpp
index 2b0450b..37156c4 100644
--- a/lib/Target/ARM/ARMInstrInfo.cpp
+++ b/lib/Target/ARM/ARMInstrInfo.cpp
@@ -52,7 +52,7 @@
return true;
case ARM::MOVr:
case ARM::tMOVr:
- assert(MI.getNumOperands() == 2 && MI.getOperand(0).isRegister() &&
+ assert(MI.getNumOperands() >= 2 && MI.getOperand(0).isRegister() &&
MI.getOperand(1).isRegister() &&
"Invalid ARM MOV instruction");
SrcReg = MI.getOperand(1).getReg();
diff --git a/lib/Target/Alpha/AlphaInstrInfo.cpp b/lib/Target/Alpha/AlphaInstrInfo.cpp
index 71bf5b0..04b08b5 100644
--- a/lib/Target/Alpha/AlphaInstrInfo.cpp
+++ b/lib/Target/Alpha/AlphaInstrInfo.cpp
@@ -33,7 +33,7 @@
oc == Alpha::CPYSTs) {
// or r1, r2, r2
// cpys(s|t) r1 r2 r2
- assert(MI.getNumOperands() == 3 &&
+ assert(MI.getNumOperands() >= 3 &&
MI.getOperand(0).isRegister() &&
MI.getOperand(1).isRegister() &&
MI.getOperand(2).isRegister() &&
diff --git a/lib/Target/IA64/IA64InstrInfo.cpp b/lib/Target/IA64/IA64InstrInfo.cpp
index 624d53a..aabdee3 100644
--- a/lib/Target/IA64/IA64InstrInfo.cpp
+++ b/lib/Target/IA64/IA64InstrInfo.cpp
@@ -30,7 +30,7 @@
MachineOpCode oc = MI.getOpcode();
if (oc == IA64::MOV || oc == IA64::FMOV) {
// TODO: this doesn't detect predicate moves
- assert(MI.getNumOperands() == 2 &&
+ assert(MI.getNumOperands() >= 2 &&
/* MI.getOperand(0).isRegister() &&
MI.getOperand(1).isRegister() && */
"invalid register-register move instruction");
diff --git a/lib/Target/PowerPC/PPCInstrInfo.cpp b/lib/Target/PowerPC/PPCInstrInfo.cpp
index 1ba701f..89b5c9c 100644
--- a/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -38,7 +38,7 @@
MachineOpCode oc = MI.getOpcode();
if (oc == PPC::OR || oc == PPC::OR8 || oc == PPC::VOR ||
oc == PPC::OR4To8 || oc == PPC::OR8To4) { // or r1, r2, r2
- assert(MI.getNumOperands() == 3 &&
+ assert(MI.getNumOperands() >= 3 &&
MI.getOperand(0).isRegister() &&
MI.getOperand(1).isRegister() &&
MI.getOperand(2).isRegister() &&
@@ -49,7 +49,7 @@
return true;
}
} else if (oc == PPC::ADDI) { // addi r1, r2, 0
- assert(MI.getNumOperands() == 3 &&
+ assert(MI.getNumOperands() >= 3 &&
MI.getOperand(0).isRegister() &&
MI.getOperand(2).isImmediate() &&
"invalid PPC ADDI instruction!");
@@ -59,7 +59,7 @@
return true;
}
} else if (oc == PPC::ORI) { // ori r1, r2, 0
- assert(MI.getNumOperands() == 3 &&
+ assert(MI.getNumOperands() >= 3 &&
MI.getOperand(0).isRegister() &&
MI.getOperand(1).isRegister() &&
MI.getOperand(2).isImmediate() &&
@@ -71,7 +71,7 @@
}
} else if (oc == PPC::FMRS || oc == PPC::FMRD ||
oc == PPC::FMRSD) { // fmr r1, r2
- assert(MI.getNumOperands() == 2 &&
+ assert(MI.getNumOperands() >= 2 &&
MI.getOperand(0).isRegister() &&
MI.getOperand(1).isRegister() &&
"invalid PPC FMR instruction");
@@ -79,7 +79,7 @@
destReg = MI.getOperand(0).getReg();
return true;
} else if (oc == PPC::MCRF) { // mcrf cr1, cr2
- assert(MI.getNumOperands() == 2 &&
+ assert(MI.getNumOperands() >= 2 &&
MI.getOperand(0).isRegister() &&
MI.getOperand(1).isRegister() &&
"invalid PPC MCRF instruction");
diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp
index 7a3dfe0..bd46cda 100644
--- a/lib/Target/X86/X86InstrInfo.cpp
+++ b/lib/Target/X86/X86InstrInfo.cpp
@@ -39,7 +39,7 @@
oc == X86::MOVSS2PSrr || oc == X86::MOVSD2PDrr ||
oc == X86::MOVPS2SSrr || oc == X86::MOVPD2SDrr ||
oc == X86::MMX_MOVD64rr || oc == X86::MMX_MOVQ64rr) {
- assert(MI.getNumOperands() == 2 &&
+ assert(MI.getNumOperands() >= 2 &&
MI.getOperand(0).isRegister() &&
MI.getOperand(1).isRegister() &&
"invalid register-register move instruction");