Relex assertions to account for additional implicit def / use operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36430 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMInstrInfo.cpp b/lib/Target/ARM/ARMInstrInfo.cpp
index 2b0450b..37156c4 100644
--- a/lib/Target/ARM/ARMInstrInfo.cpp
+++ b/lib/Target/ARM/ARMInstrInfo.cpp
@@ -52,7 +52,7 @@
return true;
case ARM::MOVr:
case ARM::tMOVr:
- assert(MI.getNumOperands() == 2 && MI.getOperand(0).isRegister() &&
+ assert(MI.getNumOperands() >= 2 && MI.getOperand(0).isRegister() &&
MI.getOperand(1).isRegister() &&
"Invalid ARM MOV instruction");
SrcReg = MI.getOperand(1).getReg();