commit 1e341729dd003ca33ecea4abf13134f20062c5f8
author Evan Cheng <evan.cheng@apple.com> Wed Apr 25 07:12:14 2007 +0000
committer Evan Cheng <evan.cheng@apple.com> Wed Apr 25 07:12:14 2007 +0000
tree 4bc71a3892c29b85687c6c6d46531aced64c4e01
parent 79b3bd395dc3303cde65e18e0524ed2f70268c99

Relex assertions to account for additional implicit def / use operands.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36430 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/IA64/IA64InstrInfo.cpp

diff --git a/lib/Target/IA64/IA64InstrInfo.cpp b/lib/Target/IA64/IA64InstrInfo.cpp
index 624d53a..aabdee3 100644
--- a/lib/Target/IA64/IA64InstrInfo.cpp
+++ b/lib/Target/IA64/IA64InstrInfo.cpp
@@ -30,7 +30,7 @@
   MachineOpCode oc = MI.getOpcode();
   if (oc == IA64::MOV || oc == IA64::FMOV) {
   // TODO: this doesn't detect predicate moves
-     assert(MI.getNumOperands() == 2 &&
+     assert(MI.getNumOperands() >= 2 &&
              /* MI.getOperand(0).isRegister() &&
              MI.getOperand(1).isRegister() && */
              "invalid register-register move instruction");