commit 1e57df3b4fd69b2a316d8931dee1b9e033ae3a9a
author Dan Gohman <djg@cray.com> Sun Feb 10 18:45:23 2008 +0000
committer Dan Gohman <djg@cray.com> Sun Feb 10 18:45:23 2008 +0000
tree 24ca65a47eb4948b2fbbc5cfeb1ebfc270bcd45e
parent b6eca4866bd51ed70374af72101bde4d7b285476

Rename MRegisterInfo to TargetRegisterInfo.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46930 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/ARM/ARMAsmPrinter.cpp

diff --git a/lib/Target/ARM/ARMAsmPrinter.cpp b/lib/Target/ARM/ARMAsmPrinter.cpp
index 609b4c4..0d10097 100644
--- a/lib/Target/ARM/ARMAsmPrinter.cpp
+++ b/lib/Target/ARM/ARMAsmPrinter.cpp
@@ -272,7 +272,7 @@
   const MachineOperand &MO = MI->getOperand(opNum);
   switch (MO.getType()) {
   case MachineOperand::MO_Register:
-    if (MRegisterInfo::isPhysicalRegister(MO.getReg()))
+    if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
       O << TM.getRegisterInfo()->get(MO.getReg()).Name;
     else
       assert(0 && "not implemented");
@@ -392,7 +392,7 @@
   const MachineOperand &MO2 = MI->getOperand(Op+1);
   const MachineOperand &MO3 = MI->getOperand(Op+2);
 
-  assert(MRegisterInfo::isPhysicalRegister(MO1.getReg()));
+  assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
   O << TM.getRegisterInfo()->get(MO1.getReg()).Name;
 
   // Print the shift opc.
@@ -401,7 +401,7 @@
     << " ";
 
   if (MO2.getReg()) {
-    assert(MRegisterInfo::isPhysicalRegister(MO2.getReg()));
+    assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
     O << TM.getRegisterInfo()->get(MO2.getReg()).Name;
     assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
   } else {
@@ -468,7 +468,7 @@
   const MachineOperand &MO2 = MI->getOperand(Op+1);
   const MachineOperand &MO3 = MI->getOperand(Op+2);
   
-  assert(MRegisterInfo::isPhysicalRegister(MO1.getReg()));
+  assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
   O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).Name;
 
   if (MO2.getReg()) {
@@ -532,7 +532,7 @@
     return;
   }
   
-  assert(MRegisterInfo::isPhysicalRegister(MO1.getReg()));
+  assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
 
   if (Modifier && strcmp(Modifier, "submode") == 0) {
     ARM_AM::AMSubMode Mode = ARM_AM::getAM5SubMode(MO2.getImm());
@@ -569,7 +569,7 @@
   }
 
   const MachineOperand &MO1 = MI->getOperand(Op);
-  assert(MRegisterInfo::isPhysicalRegister(MO1.getReg()));
+  assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
   O << "[pc, +" << TM.getRegisterInfo()->get(MO1.getReg()).Name << "]";
 }