ARM vector any_extends need to be selected to vmovl. <rdar://problem/10723651>
We have patterns for vector sext and zext operations but were missing
anyext. Without those patterns, codegen will fail when the selection DAG
has any_extend nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148568 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/test/CodeGen/ARM/vmov.ll b/test/CodeGen/ARM/vmov.ll
index be95657..0c23879 100644
--- a/test/CodeGen/ARM/vmov.ll
+++ b/test/CodeGen/ARM/vmov.ll
@@ -381,3 +381,20 @@
store <4 x float> %b, <4 x float> *%p
ret void
}
+
+; Vector any_extends must be selected as either vmovl.u or vmovl.s.
+; rdar://10723651
+define void @any_extend(<4 x i1> %x, <4 x i32> %y) nounwind ssp {
+entry:
+;CHECK: any_extend
+;CHECK: vmovl
+ %and.i186 = zext <4 x i1> %x to <4 x i32>
+ %add.i185 = sub <4 x i32> %and.i186, %y
+ %sub.i = sub <4 x i32> %add.i185, zeroinitializer
+ %add.i = add <4 x i32> %sub.i, zeroinitializer
+ %vmovn.i = trunc <4 x i32> %add.i to <4 x i16>
+ tail call void @llvm.arm.neon.vst1.v4i16(i8* undef, <4 x i16> %vmovn.i, i32 2)
+ unreachable
+}
+
+declare void @llvm.arm.neon.vst1.v4i16(i8*, <4 x i16>, i32) nounwind